IP Library Granted Patent US 12,484,232
Granted Patent B2
US 12,484,232 · App. 17/814,698 · Granted Nov 25, 2025

Ferroelectric memory device and method of fabricating the same

Inventors: Tzu-Yu Lin (Taoyuan, TW); Yao-Wen Chang (Taipei, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H10B51/30H01L23/5283H10D30/0415H10D30/701
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,484,232
App. No.
17/814,698
Granted
Nov 25, 2025
Kind
B2
Abstract

The present disclosure describes a semiconductor device having a ferroelectric memory with improved retention after cycling (RAC) memory window (MW) performance. The semiconductor device includes an interconnect structure on a substrate, a first electrode on the interconnect structure, a ferroelectric layer on the first electrode, and a second electrode on the ferroelectric layer. The first electrode includes a metal nitride conductive material having a nitrogen concentration greater than a metal concentration. The ferroelectric layer includes a ferroelectric material. The second electrode includes the metal nitride conductive material.

Claims (36)

1 . A semiconductor device, comprising:

an interconnect structure on a substrate;

a first electrode on the interconnect structure, wherein the first electrode comprises a first portion and a second portion on the first portion, wherein the first portion comprises a first metal nitride conductive material, wherein the second portion comprises a second metal nitride conductive material, and wherein a first nitrogen-to-metal ratio of the first metal nitride conductive material and a second nitrogen-to-metal ratio of the second metal nitride conductive material are different;

a ferroelectric layer on the first electrode, wherein the ferroelectric layer comprises a ferroelectric material having an orthorhombic phase, and

a second electrode on the ferroelectric layer, wherein the second electrode comprises the second metal nitride conductive material.

2 . The semiconductor device of claim 1 , wherein a nitrogen-to-metal ratio of the second metal nitride conductive material ranges from about 1.04 to about 1.2.

3 . The semiconductor device of claim 1 , wherein the second metal nitride conductive material comprises at least one of titanium nitride, tantalum nitride, hafnium nitride, zirconium nitride, vanadium nitride, and scandium nitride.

4 . The semiconductor device of claim 1 , wherein the second metal nitride conductive material comprises a (111) crystal orientation and a (200) crystal orientation, and

wherein a ratio of a first intensity of the (111) crystal orientation to a second intensity of the (200) crystal orientation ranges from about 1.6 to about 2.0.

5 . The semiconductor device of claim 1 , wherein the first portion has a first width and is on the interconnect structure and the second portion has a second width and is between the first portion and the ferroelectric layer, and wherein the second width is greater than the first width.

6 . The semiconductor device of claim 1 , wherein the ferroelectric layer comprises at least one of hafnium zirconium oxide, hafnium aluminum oxide, hafnium lanthanum oxide, hafnium cerium oxide, hafnium oxide, hafnium silicon oxide, and hafnium gadolinium oxide.

7 . The semiconductor device of claim 1 , further comprising a barrier layer between the interconnect structure and the first electrode.

8 . The semiconductor device of claim 1 , further comprising a cap layer on the second electrode.

9 . The semiconductor device of claim 1 , further comprising an additional interconnect structure electrically connected to the second electrode.

10 . A semiconductor device, comprising:

a transistor on a substrate;

an interconnect structure electrically connected to the transistor; and

a ferroelectric memory electrically connected to the interconnect structure, wherein the ferroelectric memory comprises:

first and second electrodes comprising a nitrogen-rich metal nitride conductive material having a nitrogen concentration greater than a metal concentration; and

a ferroelectric layer between the first and second electrodes.

11 . The semiconductor device of claim 10 , wherein a nitrogen-to-metal ratio of the metal nitride conductive material ranges from about 1.04 to about 1.2.

12 . The semiconductor device of claim 1 , wherein the metal nitride conductive material comprises a (111) crystal orientation and a (200) crystal orientation, and wherein a ratio of a first intensity of the (111) crystal orientation to a second intensity of the (200) crystal orientation ranges from about 1.6 to about 2.0.

13 . The semiconductor device of claim 10 , wherein the ferroelectric layer comprises at least one of hafnium zirconium oxide, hafnium aluminum oxide, hafnium lanthanum oxide, hafnium cerium oxide, hafnium oxide, hafnium silicon oxide, and hafnium gadolinium oxide.

14 . A semiconductor device, comprising:

a first interconnect structure on a substrate;

a ferroelectric memory on the first interconnect structure, wherein the ferroelectric memory comprises:

first and second electrodes comprising a metal nitride conductive material having a nitrogen concentration greater than a metal concentration in the metal nitride conductive material, wherein the metal nitride conductive material comprises a (111) crystal orientation and a (200) crystal orientation having a lower intensity than that of the (111) crystal orientation; and

a ferroelectric layer between the first and second electrodes; and

a second interconnect structure on the ferroelectric memory and in contact with the second electrode.

15 . The semiconductor device of claim 14 , wherein a nitrogen-to-metal ratio of the metal nitride conductive material ranges from about 1.04 to about 1.2.

16 . The semiconductor device of claim 14 , wherein the metal nitride conductive material comprises a (111) crystal orientation and a (200) crystal orientation, and

wherein a ratio of a first intensity of the (111) crystal orientation to a second intensity of the (200) crystal orientation ranges from about 1.6 to about 2.0.

17 . The semiconductor device of claim 14 , further comprising a barrier layer between the first interconnect structure and the first electrode.

18 . The semiconductor device of claim 1 , wherein the second nitrogen-to-metal ratio is greater than the first nitrogen-to-metal ratio.

19 . The semiconductor device of claim 10 , wherein the first electrode comprises a first portion and a second portion between the first portion and the ferroelectric layer, and wherein a first nitrogen-to-metal ratio of the first portion is less than a second nitrogen-to-metal ratio of the second portion.

20 . The semiconductor device of claim 14 , wherein the first electrode comprises a first portion and a second portion between the first portion and the ferroelectric layer, and wherein a first resistance of the first portion is greater than a second resistance of the second portion.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED ON REEL 60659 FRAME 386. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNEE. Recorded Aug 15, 2025
From: LIN, TZU-YU; CHANG, YAO-WEN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 072490/0390 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 28, 2022
From: LIN, TZU-YU; CHANG, YAO-WEN
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 060659/0386 →
Continuity (2)
Provisional Application 63314015 · Feb 25, 2022
Related Publication 20230276633A1 · Aug 31, 2023
References Cited (34)
US 6140672A · Arita · 2000 [cited by examiner]
US 10879269B1 · Zhang · 2020 [cited by examiner]
US 11152048B1 · Prasad · 2021 [cited by examiner]
US 11839088B1 · Sato · 2023 [cited by examiner]
US 11955512B1 · Rathi · 2024 [cited by examiner]
US 12108608B1 · Sato · 2024 [cited by examiner]
US 20050006680A1 · Song · 2005 [cited by examiner]
US 20070215923A1 · Tamura · 2007 [cited by examiner]
US 20090134440A1 · Kanaya · 2009 [cited by examiner]
US 20140203341A1 · Guo · 2014 [cited by examiner]
US 20160372478A1 · Ino · 2016 [cited by examiner]
US 20200105772A1 · Chen et al. · 2020 [cited by applicant]
US 20200335353A1 · Chen · 2020 [cited by examiner]
US 20200411072A1 · Zhang · 2020 [cited by examiner]
US 20200411758A1 · Lin et al. · 2020 [cited by applicant]
US 20210074708A1 · Huang · 2021 [cited by examiner]
US 20210082956A1 · Suzuki · 2021 [cited by examiner]
US 20210091095A1 · Ino · 2021 [cited by examiner]
US 20210305356A1 · Cheng et al. · 2021 [cited by applicant]
US 20210335799A1 · Lee · 2021 [cited by examiner]
US 20210343731A1 · Chen · 2021 [cited by examiner]
US 20210358925A1 · Takahashi · 2021 [cited by examiner]
US 20210366932A1 · Lee · 2021 [cited by examiner]
US 20210375888A1 · Lu · 2021 [cited by examiner]
US 20210376153A1 · Lu · 2021 [cited by examiner]
US 20230189532A1 · Müller · 2023 [cited by examiner]
US 20230284455A1 · Thareja · 2023 [cited by examiner]
DE 102020110759A1 · 2021 [cited by applicant]
KR 1020200037087A · 2020 [cited by applicant]
KR 1020210002327A · 2021 [cited by applicant]
TW 202137397A · 2021 [cited by applicant]
Athle et al. “Effects of tin top electrode texturing on ferroelectricity in hf1-x zr x o2.” ACS applied materials & interfaces 13.9 (2021): 11089-11095. [cited by applicant]
Lieberman et al. “Design of high-density plasma sources for materials processing.” Berkeley: EECS Department, University of California, 1993. IX.C Charging.—Technical Report No. UCB/ERL M93/3. 1-126. [cited by applicant]
Park et al. “Plasma-induced charging damage of a ferroelectric capacitor during interconnect metal etch.” 2000 5th International Symposium on Plasma Process-Induced Damage (IEEE Cat. No. 00TH8479). IEEE, 2000. [cited by applicant]