Three-dimensional memory device and method

1. A device comprising:

a word line extending in a first direction;

a data storage layer on a sidewall of the word line;

a channel layer on a sidewall of the data storage layer;

a back gate isolator on a sidewall of the channel layer; and

a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region separated from the channel layer by the back gate isolator, the bit line extending in a second direction, the second direction perpendicular to the first direction.

2. The device of claim 1 , wherein the first main region of the bit line is separated from the sidewall of the data storage layer by the channel layer.

3. The device of claim 1 , wherein the first main region of the bit line contacts the sidewall of the data storage layer and a single sidewall of the channel layer.

4. The device of claim 1 , wherein the first main region of the bit line contacts the sidewall of the data storage layer and a plurality of sidewalls of the channel layer.

5. The device of claim 1 further comprising:

a source line having a second main region and a second extension region, the second main region contacting the channel layer, the second extension region separated from the channel layer by the back gate isolator, the source line extending in the second direction; and

an isolation region between the source line and the bit line.

6. The device of claim 5 , wherein the isolation region, the first extension region of the bit line, and the second extension region of the source line have a same width in a third direction, the third direction perpendicular to the first direction and to the second direction.

7. The device of claim 5 , wherein the isolation region has a first width in the first direction and the back gate isolator has a second width in the first direction, the second width greater than the first width.

8. The device of claim 1 , wherein the back gate isolator comprises aluminum oxide.

9. A device comprising:

a bit line extending in a first direction, the bit line having a first T-shaped cross-section in a top-down view;

a source line extending in the first direction, the source line having a second T-shaped cross-section in the top-down view;

an isolation region between the source line and the bit line;

a word line extending in a second direction, the second direction perpendicular to the first direction;

a back gate isolator between the word line and each of the isolation region, a first portion of the bit line, and a second portion of the source line;

a channel layer between the back gate isolator and the word line; and

a data storage layer between the channel layer and the word line.

10. The device of claim 9 , wherein the isolation region has a first width in the second direction, and the back gate isolator has a second width in the second direction, the second width greater than the first width.

11. The device of claim 10 , wherein the channel layer has the second width in the second direction.

12. The device of claim 10 , wherein the channel layer has a third width in the second direction, and a combination of the bit line, the source line, and the isolation region has a fourth width in the second direction, the third width greater than the second width and less than the fourth width.

13. The device of claim 10 , wherein the channel layer has a third width in the second direction, and a combination of the bit line, the source line, and the isolation region has the third width in the second direction, the third width greater than the second width.

14. The device of claim 10 further comprising:

a source line interconnect over and connected to the source line; and

a bit line interconnect over and connected to the bit line.

15. The device of claim 10 , wherein the back gate isolator comprises aluminum oxide.

16. A device comprising:

a word line;

a memory layer on a sidewall of the word line;

a channel layer on a sidewall of the memory layer;

a back gate layer on a sidewall of the channel layer;

an isolation region on a sidewall of the back gate layer;

a bit line having a first main region and a first extension region, the back gate layer disposed between the channel layer and the first extension region of the bit line in a top-down view; and

a source line having a second main region and a second extension region, the back gate layer disposed between the channel layer and the second extension region of the source line in the top-down view, the bit line and the source line disposed at opposing sides of the isolation region in the top-down view.

17. The device of claim 16 , wherein the first main region of the bit line contacts the sidewall of the channel layer but not the sidewall of the memory layer, and the second main region of the source line contacts the sidewall of the channel layer but not the sidewall of the memory layer.

18. The device of claim 16 , wherein the first main region of the bit line contacts the sidewall of the channel layer and the sidewall of the memory layer, and the second main region of the source line contacts the sidewall of the channel layer and the sidewall of the memory layer.

19. The device of claim 16 , wherein the first main region of the bit line contacts the sidewall of the memory layer but not the sidewall of the channel layer, and the second main region of the source line contacts the sidewall of the memory layer but not the sidewall of the channel layer.

20. The device of claim 16 , wherein the back gate layer comprises aluminum oxide.