Memory devices including oxide semiconductor
A method of forming a device comprises forming dielectric structures over other dielectric structures overlying conductive contact structures, the dielectric structures separated from one another by trenches and laterally extending orthogonal to the other dielectric structures and the conductive contact structures. Conductive gate structures are formed on exposed side surfaces of the dielectric structures within the trenches. Dielectric oxide structures are formed on exposed side surfaces of the conductive gate structures within the trenches. Exposed portions of the other dielectric structures are removed to form isolation structures. Semiconductive pillars are formed on exposed side surfaces of the dielectric oxide structures and the isolation structures within the trenches. The semiconductive pillars are in electrical contact with the conductive contact structures. Additional conductive contact structures are formed on upper surfaces of the semiconductive pillars. A device, a memory device, and an electronic system are also described.
1. A memory device, comprising:
an access line;
a data line;
a source line;
memory cells between the data line and the source line, each memory cell comprising:
a vertical access device electrically coupled to the access line, the vertical access device comprising:
a channel pillar comprising at least one oxide semiconductor material,
a source contact vertically between the source line and the channel pillar,
a drain contact on the channel pillar,
a gate electrode laterally neighboring the channel pillar and electrically coupled to
the access line, and a gate dielectric material between the channel pillar and the gate electrode; and
a memory element between the data line and the drain contact of the vertical access device; and
an air gap located between the gate electrode of the vertical access device of one of the memory cells and the gate electrode of the vertical access device of an additional one of the memory cells.
2. The memory device of claim 1 , wherein the vertical
access device of each memory cell further comprises:
another gate electrode laterally neighboring the channel pillar and electrically coupled to the access line; and
another gate dielectric material between the channel pillar and the another gate electrode.
3. The memory device of claim 1 , wherein one or more of the source contact and the drain contact comprises two or more of titanium, titanium nitride, ruthenium, tungsten, and indium oxide.
4. The memory device of claim 3 , wherein a material composition of the source contact is substantially the same as a material composition of the drain contact.
5. The memory device of claim 3 , wherein:
the channel pillar is directly vertically adjacent the source contact and the drain contact; and
the channel pillar comprises one or more of indium oxide, indium zinc oxide, indium gallium zinc oxide, indium gallium silicon oxide, and indium tungsten oxide.
6. The memory device of claim 1 , wherein:
the gate electrode and the gate dielectric material are each on an upper surface of an isolation structure comprising dielectric nitride material, the isolation structure on an upper surface of the source contact; and
the channel pillar is on the upper surface of the source contact and is directly horizontally adjacent side surfaces of the gate dielectric material and the isolation structure.
7. The memory device of claim 6 , wherein the gate electrode is substantially confined with a horizontal area of the isolation structure.
8. The memory device of claim 1 , wherein a lower surface of the drain contact directly physically contacts each of an upper surface of the channel pillar and an upper surface of the gate dielectric material substantially coplanar with the upper surface of the channel pillar.
9. The memory device of claim 1 , wherein:
a lower boundary of the air gap is substantially coplanar with each of:
a lower surface of the gate electrode of the vertical access device of the one of the memory cells; and
a lower surface of the gate electrode of the vertical access device of the additional one of the memory cells; and
an upper boundary of the air gap vertically underlies each of:
an upper surface of the gate electrode of the vertical access device of the one of the memory cells; and
an upper surface of the gate electrode of the vertical access device of the additional one of the memory cells.