Apparatuses, systems, and methods for memory module data drivers
Apparatuses, systems, and methods for memory module data drives. A memory module includes a number of memory devices as well as module logic. Each memory device provides data by driving voltages along a data bus with a data bus driver of the memory device. An output driver, which is located on the module logic receives the voltages along the data bus and drives voltages of an external data terminal to output the data. The output driver may have a greater drive strength than the data bus driver.
1. An apparatus comprising:
output terminals;
a first memory device configured to provide data along a first data bus;
a second memory device configured to provide data along a second data bus;
module logic configured to receive the data from the first data bus and the second data bus, the module logic including output drivers configured to drive a voltage of the output terminals based on the received data from the first data bus and the second data bus, wherein the output drivers comprises a first output driver associated with the first memory device, the first output driver including a first synchronizer circuit; and
a delay circuit configured to provide a delayed clock signal, wherein the first synchronization circuit is configured to synchronize the voltage to the delayed clock signal.
2. The apparatus of claim 1 , wherein the output drivers are not on the first memory device or the second memory device.
3. The apparatus of claim 1 , wherein the module logic includes module settings register, and wherein a drive strength of the output drivers is set based on a setting of the module settings register.
4. The apparatus of claim 1 , wherein each of the output drivers includes a termination circuit.
5. The apparatus of claim 1 , wherein the first memory device includes a first data bus driver, the second memory device includes a second data bus driver, and wherein a drive strength of the output drivers is greater than a drive strength of the first data bus driver or the second data bus driver.
6. An apparatus comprising:
output terminals;
a first memory device configured to provide data along a first data bus;
a second memory device configured to provide data along a second data bus;
module logic configured to receive the data from the first data bus and the second data bus, the module logic including output drivers configured to drive a voltage of the output terminals based on the received data from the first data bus and the second data bus,
wherein the output drivers include:
a first output driver associated with the first memory, the first output driver including a first synchronizer circuit; and
a second output driver associated with the second memory, the second output driver including a second synchronizer circuit,
the apparatus further comprising a delay circuit shared by the first synchronizer circuit and the second synchronizer circuit.
7. An apparatus comprising:
output terminals;
a first memory device configured to provide data along a first data bus;
a second memory device configured to provide data along a second data bus;
module logic configured to receive the data from the first data bus and the second data bus, the module logic including output drivers configured to drive a voltage of the output terminals based on the received data from the first data bus and the second data bus, wherein the first memory device includes a first data bus driver, the second memory device includes a second data bus driver, and wherein a drive strength of the output drivers is greater than a drive strength of the first data bus driver or the second data bus driver, wherein the first data bus driver includes a first serializer circuit and the second data bus driver includes a second serializer circuit.
8. An apparatus comprising:
a memory device comprising a data bus driver configured to drive a voltage along a data bus;
an output driver configured to receive the voltage along the data bus and drive a voltage of an external data terminal based on the voltage along the data bus, wherein the output driver is not located on the memory device; and
a delay circuit configured to provide a delayed clock signal, wherein the delay circuit is not located on the memory device, and wherein the output driver comprises a synchronizer circuit configured to synchronize the voltage along the data bus to the delayed clock signal.
9. The apparatus of claim 8 , wherein the memory device and the output driver are packaged on a memory module.
10. The apparatus of claim 8 , further comprising a second memory device comprising a second data bus driver configured to drive a second voltage along a second data bus wherein the second memory device and the first memory device are on a memory module; and
a second output driver configured to receive the second voltage along the second data bus and drive a voltage of a second output terminal based on the second voltage along the data bus, wherein the output driver is not located on the second memory device, and wherein the output driver and the second output driver are part of a module logic circuit of the memory module.
11. The apparatus of claim 8 , wherein a drive strength of the output driver is greater than a drive strength of the data bus driver.
12. The apparatus of claim 8 , further comprising a module settings register, wherein a drive strength of the output driver is determined by a setting of the module settings register.
13. The apparatus of claim 8 , wherein the memory device is further configured to provide a data strobe clock signal, and wherein the data strobe clock signal is provided to an external data strobe terminal.
14. A method comprising:
reading data from a memory array of a memory device;
driving voltages along a data bus with a data bus driver of the memory device based on the read data;
receiving the voltages along the data bus at an output driver, wherein the output driver is not on the memory device;
driving voltages of output terminals with the output driver based on the received voltages along the data bus;
delaying a clock signal; and
synchronizing the voltages along the data bus to the delayed clock signal with the output driver.
15. The method of claim 14 , further comprising:
driving the voltages along the data bus with a first drive strength; and
driving the voltages of the output terminals with a second drive strength greater than the first drive strength.
16. The method of claim 14 , further comprising:
reading second data from a second memory array of a second memory device;
driving second voltages along a second data bus with a second data bus driver of the second memory device based on the second read data; and
receiving the voltages along the second data bus at a second output driver, wherein the second output driver is not on the second memory device.
17. The method of claim 16 , further comprising:
synchronizing the second voltages along the second data bus to the delayed clock signal with the second output driver.
18. The method of claim 14 , further comprising setting a drive strength of the output driver based on settings in a module settings register.
19. The method of claim 14 , further comprising:
serializing the data with the data bus driver of the memory device.