IP Library Granted Patent US 11,675,533
Granted Patent B2
US 11,675,533 · App. 17/825,905 · Granted Jun 13, 2023

One-shot state transition probability encoder and decoder

Inventors: Zheng Wang (Longmont, CO); Marcus Marrow (San Jose, CA); Jason Bellorado (San Jose, CA)
Assignee: Seagate Technology LLC
G06F3/0656G06F3/0604G06F3/0673G06F18/295H03M13/3961H03M13/45
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Quick Facts
Patent No.
US 11,675,533
App. No.
17/825,905
Granted
Jun 13, 2023
Kind
B2
Abstract

A one-shot state transition decoder receives a codeword having N-bits. The decoder reads a first D-bits of the codeword to determine a stitching location d within the codeword. The stitching location identifies a start bit of unencoded data in the codeword. The codeword is decoded into an output buffer for user data of L bits, where N>L. Parameters of the decoder are set before the decoding, including setting a length of the codeword to N−L+d and a number of expected decoded bits to d. The decoding including decoding the d bits based on a set of state transition probabilities and copying decoded bits into the output buffer, the unencoded data being copied to the end of the output buffer.

Claims (28)

1. A method, comprising:

receiving a signal comprising an N-bit codeword at a processing circuit comprising a modulation decoder;

reading a first D-bits of the codeword to determine a stitching location d within the codeword, the stitching location identifying a start bit of unencoded data in the codeword;

performing a decoding of the codeword into an output buffer for user data comprising L bits, L<N, wherein parameters of the modulation decoder are set before the decoding, the setting of the parameters including setting a number of expected decoded bits to d and a length of the codeword to N−L+d, the decoding including decoding the d bits based on a set of state transition probabilities and copying decoded bits into the output buffer;

copying the unencoded data to an end of the output buffer; and

sending the output buffer as recovered user data to a host.

2. The method of claim 1 , wherein based on the first D-bits being a predetermined pattern, there are no unencoded bits in the codeword and the decoding comprises decoding all N−D bits of the codeword excluding the first D-bits.

3. The method of claim 2 , wherein the predetermined pattern is all ones.

4. The method of claim 1 , wherein the set of state transition probabilities comprise a set of Markov state transition probabilities used in an encoding of the codeword.

5. The method of claim 4 , wherein the encoding implements probabilistic constraints that minimize certain patterns in generated codeword sequences without eliminating the certain patterns.

6. The method of claim 4 , wherein the encoding implements deterministic constraints that eliminate certain patterns in generated codeword sequences.

7. The method of claim 1 , wherein the codeword is received from a low-density parity check (LDPC) decoder.

8. The method of claim 1 , further comprising:

finding a first unencoded bit of the unencoded data; and

if the first unencoded bit is equal to a first value, perform a final bit carry operation when decoding the codeword, otherwise do not perform the final bit carry operation if the first unencoded bit is not equal to the first value.

9. An apparatus, comprising a processing circuit, the processing circuit comprising:

an error correction decoder that decodes an N-bit codeword based on data read from a storage media; and

a modulation decoder operable to:

receive a signal comprising the codeword from the storage media;

read a first D-bits of the codeword to determine a stitching location d within the codeword, the stitching location identifying a start bit of unencoded data in the codeword;

perform a decoding of the codeword into an output buffer for user data comprising L bits, L<N, wherein parameters of the modulation decoder are set before the decoding, the setting of the parameters including setting a number of expected decoded bits to d and a length of the codeword to N−L+d, the decoding including decoding the d bits based on a set of state transition probabilities and copying decoded bits into the output buffer;

copy the unencoded data to an end of the output buffer; and

sending the output buffer as recovered user data to a host.

10. The apparatus of claim 9 , wherein based on the first D-bits being a predetermined pattern, there are no unencoded bits in the codeword and the decoding comprises decoding all N−D bits of the codeword excluding the first D-bits.

11. The apparatus of claim 9 , wherein the set of state transition probabilities comprise a set of Markov state transition probabilities used in an encoding of the codeword.

12. The apparatus of claim 11 , wherein the encoding implements probabilistic constraints that minimizes certain patterns in generated codeword sequences without eliminating the certain patterns.

13. The apparatus of claim 11 , wherein the encoding implements deterministic constraints that eliminates certain patterns in generated codeword sequences.

14. The apparatus of claim 9 , wherein the error correction decoder comprises a low-density parity check (LDPC) decoder.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 22, 2024
From: SEAGATE TECHNOLOGY LLC; SEAGATE SINGAPORE INTERNATIONAL HEADQUARTERS PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 067489/0509 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 24, 2023
From: WANG, ZHENG; MARROW, MARCUS; BELLORADO, JASON
To: SEAGATE TECHNOLOGY LLC
Reel/Frame 065320/0019 →