Electronic circuit and method of error correction

1. An electronic circuit, comprising:

a time-to-digital converter (TDC), configured to generate a first signal;

an error cancelation circuit, configured to evaluate a majority of bit values of at least a portion of the first signal to generate a second signal, wherein the number of transitions within the second signal is less than the number of transitions within the first signal, and a first fractional phase error value determined by the first signal is greater than a second fractional phase error value determined by the second signal;

an adder, connected to the error cancelation circuit and configured to receive the second fractional phase error value; and

a digital filter, connected to the adder.

2. The electronic circuit of claim 1 , wherein the N th bit of the second signal is determined based on odd number of bits of the first signal, and the odd number of bits comprise the N th bit of the first signal and the even number of bits of the first signal adjacent to the N th bit of the first signal.

3. The electronic circuit of claim 2 , wherein the N th bit of the second signal is determined by the bit that appears most often among the (N−1) th bit, N th bit, and (N+1) th bit of the first signal.

4. The electronic circuit of claim 3 , wherein when the (N−1) th bit of the first signal has a value of X, the N th bit of the first signal has a value of Y, and the (N+1) th bit of the first signal has a value of Z, the N th bit of the second signal, F, is determined by:

F=X·Y+X·Z+Y·Z.

5. The electronic circuit of claim 2 , wherein the N th bit of the second signal is determined by the bit that appears most often among the (N−2) th bit, (N−1) th bit, N th bit, (N+1) th bit, and (N+2) th bit of the first signal.

6. The electronic circuit of claim 5 , wherein when the (N−2) th bit of the first signal has a value of A, the (N−1) th bit of the first signal has a value of B, the N th bit of the first signal has a value of C, the (N+1) th bit of the first signal has a value of D, and the (N+2) th bit of the first signal has a value of E, the N th bit of the second signal, F, is determined by:

F =( A·B·C )+( B·C·D )+( C·D·E )+( A·B·D )+( A·B·E )+( B·C·E )+( A·C·D )+( A·D·E )+( B·D·E )+( A·C·E ).

7. The electronic circuit of claim 1 , wherein the first bit of the second signal is equal to the first bit of the first signal, and the last bit of the second signal is equal to the last bit of the first signal.

8. The electronic circuit of claim 1 , wherein the TDC further comprises

a set of inverters connected in series; and

a set of flip-flops, each flip-flop connected with the corresponding inverter,

wherein an input of the first one of the set of inverters receives a first clock signal, and each of the set of flip-flops receives a second clock signal.

9. A method of error correction for an electronic circuit, comprising:

receiving a first set of bits;

evaluating a first rising edge and a first falling edge, wherein the first rising edge corresponds to the most recent transition from a low bit value to a high bit value, and the first falling edge corresponds to the most recent transition from a high bit value to a low bit value;

determining whether a first difference between the first rising edge and the first falling edge is smaller than or equal to a first threshold value; and

assigning twice of the first difference as a period of the first set of bits when the first difference is not smaller than or equal to the first threshold value.

10. The method of claim 9 , further comprising:

evaluating a second rising edge and a second falling edge, wherein the second rising edge corresponds to the second most recent transition from low bit value to high bit value, and the second falling edge corresponds to the second most recent transition from high bit value to low bit value.

11. The method of claim 10 , further comprising:

determining a maximum of twice of a second difference between the second rising edge and the first falling edge and twice of a third difference between the first rising edge and the second falling edge; and

assigning the maximum as the period when the first difference is smaller than or equal to the first threshold value.

12. The method of claim 9 , wherein the first rising edge is the rising time of the first set of bits.

13. The method of claim 11 , further comprising:

determining whether a fourth difference between the second rising edge and the first rising edge is smaller than or equal to a second threshold value; and

assigning twice of the third difference as the period when a first condition is met, wherein the first condition comprises the first difference being smaller than or equal to the first threshold value and the fourth difference is smaller than or equal to the second threshold value.

14. The method of claim 13 , further comprising:

determining whether a fifth difference between the second falling edge and the first falling edge is smaller than or equal to a third threshold value when the first condition is not met; and

assigning twice of the second difference as the period when a second condition is met, wherein the second condition comprises the first difference being smaller than or equal to the first threshold value and the fifth difference is smaller than or equal to the third threshold value.

15. The method of claim 14 , wherein the second threshold value is equal to the first threshold value, and the third threshold value is equal to the first threshold value.

16. The method of claim 14 , further comprising:

assigning twice of the first difference as the period when the second condition is not met.

17. A method of error correction for an electronic circuit, comprising:

generating a first signal by a time-to-digital converter (TDC);

evaluating a majority of bit values of at least a portion of the first signal to generate a second signal by an error cancelation circuit, wherein the number of transitions within the second signal is less than the number of transitions within the first signal, and a first fractional phase error value determined by the first signal is greater than a second fractional phase error value determined by the second signal; and

receiving the second fractional phase error value by an adder connected to a digital filter.

18. The method of claim 17 , further comprising:

determining the N th bit of the second signal based on odd number of bits of the first signal, wherein the odd number of bits comprise the N th bit of the first signal and the even number of bits of the first signal adjacent to the N th bit of the first signal.

19. The method of claim 18 , wherein the N th bit of the second signal is determined by the bit that appears most often among the (N−1) th bit, N th bit, and (N+1) th bit of the first signal.

20. The method of claim 17 , wherein the first bit of the second signal is equal to the first bit of the first signal, and the last bit of the second signal is equal to the last bit of the first signal.