IP Library › Granted Patent US 12,450,513

Granted Patent B2

US 12,450,513 · App. 17/828,556 · Granted Oct 21, 2025

Quantum controller validation

Inventors: Ori Weber (Tel Aviv, IL); Tamar Ben Haim Sembira (Tel Aviv, IL); Lior Ella (Tel Aviv, IL); Yonatan Cohen (Tel Aviv, IL); Nissim Ofek (Tel Aviv, IL); Itamar Sivan (Tel Aviv, IL)

Assignee: Q.M Technologies Ltd.

G06N10/20 G06N10/80

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Quick Facts

Patent No.: US 12,450,513
App. No.: 17/828,556
Granted: Oct 21, 2025
Kind: B2

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Abstract

Quantum algorithms are performed via a quantum computer, by generating a quantum control pulse in a quantum controller and transmitting the quantum control pulse to a quantum processor. The quantum control pulse interacts with a qubit in the quantum processor. Within the quantum controller, a pulse processor generates a plurality of raw pulses that are modified by a front end hardware module. During the normal operation of the quantum controller, samples of the raw and/or modified pulses may be selected and saved to memory. During a design for validation (DFV) mode, the proper operation of the quantum controller is determined according to a simulation of the quantum controller and the saved samples. The DFV mode may be performed in parallel with normal operation without affecting the resources of the quantum controller.

Claims (266)

1. A system comprising:

a quantum controller comprising:

a plurality of software components;

a plurality of hardware components; and

a behavioral model, wherein:

the plurality of software components are configured to selectively interact with the plurality of hardware components and/or the behavioral model,

an interaction between the plurality of software components and the plurality of hardware components is independent of a parallel interaction between the plurality of software components and the behavioral model,

the plurality of software components are operable to generate a plurality of pulses that control an interaction with one or more quantum elements,

the plurality of hardware components comprise a front end module (FEM) operable to modify the plurality of pulses prior to the interaction with one or more quantum elements,

the quantum controller comprises a memory operable to store data extracted from the plurality of hardware components,

the data extracted from the plurality of hardware components corresponds to the modified plurality of pulses,

the quantum controller comprises a computer processing unit (CPU) configured to simulate the plurality of software components and the front end module, and

the CPU is operable to validate the plurality of software components and the front end module according to the simulation.

2. The system of claim 1 , wherein:

the quantum controller comprises a design for validation (DFV) controller operable to extract data from the plurality of hardware components for validation.

3. The system of claim 1 , wherein:

each pulse of the plurality of pulses comprises a plurality of consecutive analog values,

the plurality of consecutive analog values, once modified, are sent to one or more digital to analog converters (DACs), and

the data extracted from the plurality of hardware components comprises only one analog value out of several consecutive analog values.

4. The system of claim 1 , wherein:

the plurality of hardware components comprise hardware logic configured to modify analog values from the plurality of software components,

the plurality of hardware components comprise hardware logic configured to modify digital markers from the plurality of software components, and

the quantum controller comprises a plurality of digital-to-analog converters (DACs).

5. The system of claim 1 , wherein:

the plurality of hardware components comprises a buffer operable to receive a plurality of analog values from the plurality of software components,

the system comprises a memory operable to store one or more analog values of the plurality of analog values, and

the behavioral model is operable to simulate the one or more analog values for validation of the stored one or more analog values.

6. The system of claim 1 , wherein:

the plurality of hardware components comprises a modulator operable to modulate a plurality of analog values from the plurality of software components, thereby generating a plurality of modulated analog values,

the system comprises a memory operable to store one or more modulated analog values of the plurality of modulated analog values, and

the behavioral model is operable to simulate the one or more modulated analog values for validation of the stored one or more modulated analog values.

7. The system of claim 1 , wherein:

the plurality of hardware components comprises a router operable to route a plurality of analog values to a digital to analog converter (DAC), thereby generating a plurality of routed analog values,

the system comprises a memory operable to store one or more routed analog values of the plurality of routed analog values, and

the behavioral model is operable to simulate the one or more routed analog values for validation of the stored one or more routed analog values.

8. The system of claim 1 , wherein:

the plurality of hardware components comprises one or more filters operable to filter a plurality of analog values, thereby generating a plurality of filtered analog values,

the system comprises a memory operable to store one or more filtered analog values of the plurality of filtered analog values, and

the behavioral model is operable to simulate the one or more filtered analog values for validation of the stored one or more filtered analog values.

9. The system of claim 1 , wherein:

the plurality of hardware components comprises a buffer operable to receive a plurality of digital markers from the plurality of software components,

the system comprises a memory operable to store one or more digital markers of the plurality of digital markers, and

the behavioral model is operable to simulate the one or more digital markers for validation of the stored one or more digital markers.

10. The system of claim 1 , wherein:

the plurality of hardware components comprises a convolution device operable to convolve a plurality of digital markers with a dynamic kernel, thereby generating a plurality of convolved digital markers,

the system comprises a memory operable to store one or more convolved digital markers of the plurality of convolved digital markers, and

the behavioral model is operable to simulate the one or more convolved digital markers for validation of the stored one or more convolved digital markers.

11. The system of claim 1 , wherein:

the plurality of hardware components comprises a variable delay operable to delay a plurality of digital markers, thereby generating a plurality of delayed digital markers,

the system comprises a memory operable to store one or more delayed digital markers of the plurality of delayed digital markers, and

the behavioral model is operable to simulate the one or more delayed digital markers for validation of the stored one or more delayed digital markers.

12. The system of claim 1 , wherein:

the plurality of hardware components comprises one or more polarity generators operable to set the polarity of a plurality of digital markers, thereby generating a plurality of polarized digital markers,

the system comprises a memory operable to store one or more polarized digital markers of the plurality of polarized digital markers, and

the behavioral model is operable to simulate the one or more polarized digital markers for validation of the stored one or more polarized digital markers.

13. A method comprising:

selecting, via a hardware abstraction layer (HAL), a design for validation (DFV) test of a quantum controller;

orchestrating an interaction between a plurality of software components of the quantum controller and a plurality of hardware components of the quantum controller;

independently orchestrating a parallel interaction between the plurality of software components of the quantum controller and a behavioral model of the quantum controller;

generating, via the plurality of software components, a plurality of pulses that control an interaction with one or more quantum elements;

modifying, via the plurality of hardware components, the plurality of pulses prior to the interaction with one or more quantum elements;

storing, in a memory, data extracted from the plurality of hardware components;

simulating, in a computer processing unit (CPU) of the quantum controller, the plurality of software components and the plurality of hardware components; and

validating the plurality of software components and the plurality of hardware components according to the simulation and the stored data.

14. The method of claim 13 , wherein the method comprises:

extracting, via a design for validation (DFV) controller, data from the plurality of hardware components for validation.

15. The method of claim 13 , wherein the method comprises:

extracting the data from the plurality of hardware components, wherein the data comprises only one analog value out of several consecutive analog values.

16. The method of claim 13 , wherein the method comprises:

modifying analog values from the plurality of software components;

modifying digital markers from the plurality of software components; and

sending the modified analog values to a plurality of digital-to-analog converters (DACs) in coordination with outputting the modified digital markers.

17. The method of claim 13 , wherein the method comprises:

buffering a plurality of analog values from the plurality of software components;

storing one or more analog values of the plurality of analog values; and

simulating the one or more analog values for validation of the stored one or more analog values.

18. The method of claim 13 , wherein the method comprises:

modulating a plurality of analog values from the plurality of software components, thereby generating a plurality of modulated analog values;

storing one or more modulated analog values of the plurality of modulated analog values; and

simulating the one or more modulated analog values for validation of the stored one or more modulated analog values.

19. The method of claim 13 , wherein the method comprises:

routing a plurality of analog values to a digital to analog converter (DAC), thereby generating a plurality of routed analog values;

storing one or more routed analog values of the plurality of routed analog values; and

simulating the one or more routed analog values for validation of the stored one or more routed analog values.

20. The method of claim 13 , wherein the method comprises:

filtering a plurality of analog values, thereby generating a plurality of filtered analog values;

storing one or more filtered analog values of the plurality of filtered analog values; and

simulating the one or more filtered analog values for validation of the stored one or more filtered analog values.

21. The method of claim 13 , wherein the method comprises:

buffering a plurality of digital markers from the plurality of software components;

storing one or more digital markers of the plurality of digital markers; and

simulating the one or more digital markers for validation of the stored one or more digital markers.

22. The method of claim 13 , wherein the method comprises:

convolving a plurality of digital markers with a dynamic kernel, thereby generating a plurality of convolved digital markers;

storing one or more convolved digital markers of the plurality of convolved digital markers; and

simulating the one or more convolved digital markers for validation of the stored one or more convolved digital markers.

23. The method of claim 13 , wherein the method comprises:

delaying a plurality of digital markers, thereby generating a plurality of delayed digital markers;

storing one or more delayed digital markers of the plurality of delayed digital markers; and

simulating the one or more delayed digital markers for validation of the stored one or more delayed digital markers.

24. The method of claim 13 , wherein the method comprises:

setting the polarity of a plurality of digital markers, thereby generating a plurality of polarized digital markers;

storing one or more polarized digital markers of the plurality of polarized digital markers; and

simulating the one or more polarized digital markers for validation of the stored one or more polarized digital markers.

25. A system comprising:

a quantum controller comprising:

a plurality of software components;

a plurality of hardware components; and

a behavioral model, wherein:

the plurality of software components are configured to selectively interact with the plurality of hardware components and/or the behavioral model,

the system comprises a memory operable to store one or more convolved digital markers of the plurality of convolved digital markers, and

the behavioral model is operable to simulate the one or more convolved digital markers for validation of the stored one or more convolved digital markers.

26. The system of claim 25 , wherein:

the quantum controller comprises a design for validation (DFV) controller operable to extract data from the plurality of hardware components for validation.

27. The system of claim 25 , wherein:

the plurality of hardware components comprise hardware logic configured to modify analog values from the plurality of software components,

the plurality of hardware components comprise hardware logic configured to modify digital markers from the plurality of software components, and

the quantum controller comprises a plurality of digital-to-analog converters (DACs).

28. The system of claim 25 , wherein:

the plurality of hardware components comprises a buffer operable to receive a plurality of analog values from the plurality of software components,

the system comprises a memory operable to store one or more analog values of the plurality of analog values, and

the behavioral model is operable to simulate the one or more analog values for validation of the stored one or more analog values.

29. The system of claim 25 , wherein:

the system comprises a memory operable to store one or more modulated analog values of the plurality of modulated analog values, and

the behavioral model is operable to simulate the one or more modulated analog values for validation of the stored one or more modulated analog values.

30. The system of claim 25 , wherein:

the plurality of hardware components comprises a router operable to route a plurality of analog values to a digital to analog converter (DAC), thereby generating a plurality of routed analog values,

the system comprises a memory operable to store one or more routed analog values of the plurality of routed analog values, and

the behavioral model is operable to simulate the one or more routed analog values for validation of the stored one or more routed analog values.

31. The system of claim 25 , wherein:

the plurality of hardware components comprises one or more filters operable to filter a plurality of analog values, thereby generating a plurality of filtered analog values,

the system comprises a memory operable to store one or more filtered analog values of the plurality of filtered analog values, and

the behavioral model is operable to simulate the one or more filtered analog values for validation of the stored one or more filtered analog values.

32. The system of claim 25 , wherein:

the plurality of hardware components comprises a buffer operable to receive a plurality of digital markers from the plurality of software components,

the system comprises a memory operable to store one or more digital markers of the plurality of digital markers, and

the behavioral model is operable to simulate the one or more digital markers for validation of the stored one or more digital markers.

33. The system of claim 25 , wherein:

the plurality of hardware components comprises a variable delay operable to delay a plurality of digital markers, thereby generating a plurality of delayed digital markers,

the system comprises a memory operable to store one or more delayed digital markers of the plurality of delayed digital markers, and

the behavioral model is operable to simulate the one or more delayed digital markers for validation of the stored one or more delayed digital markers.

34. The system of claim 25 , wherein:

the system comprises a memory operable to store one or more polarized digital markers of the plurality of polarized digital markers, and

the behavioral model is operable to simulate the one or more polarized digital markers for validation of the stored one or more polarized digital markers.

35. A method comprising:

selecting, via a hardware abstraction layer (HAL), a design for validation (DFV) test of a quantum controller;

orchestrating an interaction between a plurality of software components of the quantum controller and a plurality of hardware components of the quantum controller;

independently orchestrating a parallel interaction between the plurality of software components of the quantum controller and a behavioral model of the quantum controller;

convolving a plurality of digital markers with a dynamic kernel, thereby generating a plurality of convolved digital markers;

storing one or more convolved digital markers of the plurality of convolved digital markers; and

simulating the one or more convolved digital markers for validation of the stored one or more convolved digital markers.

36. The method of claim 35 , wherein the method comprises:

extracting, via a design for validation (DFV) controller, data from the plurality of hardware components for validation.

37. The method of claim 35 , wherein the method comprises:

modifying analog values from the plurality of software components;

modifying digital markers from the plurality of software components; and

sending the modified analog values to a plurality of digital-to-analog converters (DACs) in coordination with outputting the modified digital markers.

38. The method of claim 35 , wherein the method comprises:

buffering a plurality of analog values from the plurality of software components;

storing one or more analog values of the plurality of analog values; and

simulating the one or more analog values for validation of the stored one or more analog values.

39. The method of claim 35 , wherein the method comprises:

modulating a plurality of analog values from the plurality of software components, thereby generating a plurality of modulated analog values;

storing one or more modulated analog values of the plurality of modulated analog values; and

simulating the one or more modulated analog values for validation of the stored one or more modulated analog values.

40. The method of claim 35 , wherein the method comprises:

routing a plurality of analog values to a digital to analog converter (DAC), thereby generating a plurality of routed analog values;

storing one or more routed analog values of the plurality of routed analog values; and

simulating the one or more routed analog values for validation of the stored one or more routed analog values.

41. The method of claim 35 , wherein the method comprises:

filtering a plurality of analog values, thereby generating a plurality of filtered analog values;

storing one or more filtered analog values of the plurality of filtered analog values; and

simulating the one or more filtered analog values for validation of the stored one or more filtered analog values.

42. The method of claim 35 , wherein the method comprises:

buffering a plurality of digital markers from the plurality of software components;

storing one or more digital markers of the plurality of digital markers; and

simulating the one or more digital markers for validation of the stored one or more digital markers.

43. The method of claim 35 , wherein the method comprises:

delaying a plurality of digital markers, thereby generating a plurality of delayed digital markers;

storing one or more delayed digital markers of the plurality of delayed digital markers; and

simulating the one or more delayed digital markers for validation of the stored one or more delayed digital markers.

44. The method of claim 35 , wherein the method comprises:

setting the polarity of a plurality of digital markers, thereby generating a plurality of polarized digital markers;

storing one or more polarized digital markers of the plurality of polarized digital markers; and

simulating the one or more polarized digital markers for validation of the stored one or more polarized digital markers.

45. A system comprising:

a quantum controller comprising:

a plurality of software components;

a plurality of hardware components; and

a behavioral model, wherein:

the plurality of software components are configured to selectively interact with the plurality of hardware components and/or the behavioral model,

the system comprises a memory operable to store one or more polarized digital markers of the plurality of polarized digital markers, and

the behavioral model is operable to simulate the one or more polarized digital markers for validation of the stored one or more polarized digital markers.

46. The system of claim 45 , wherein:

the quantum controller comprises a design for validation (DFV) controller operable to extract data from the plurality of hardware components for validation.

47. The system of claim 45 , wherein:

the plurality of hardware components comprise hardware logic configured to modify analog values from the plurality of software components,

the plurality of hardware components comprise hardware logic configured to modify digital markers from the plurality of software components, and

the quantum controller comprises a plurality of digital-to-analog converters (DACs).

48. The system of claim 45 , wherein:

the plurality of hardware components comprises a buffer operable to receive a plurality of analog values from the plurality of software components,

the system comprises a memory operable to store one or more analog values of the plurality of analog values, and

the behavioral model is operable to simulate the one or more analog values for validation of the stored one or more analog values.

49. The system of claim 45 , wherein:

the system comprises a memory operable to store one or more modulated analog values of the plurality of modulated analog values, and

the behavioral model is operable to simulate the one or more modulated analog values for validation of the stored one or more modulated analog values.

50. The system of claim 45 , wherein:

the plurality of hardware components comprises a router operable to route a plurality of analog values to a digital to analog converter (DAC), thereby generating a plurality of routed analog values,

the system comprises a memory operable to store one or more routed analog values of the plurality of routed analog values, and

the behavioral model is operable to simulate the one or more routed analog values for validation of the stored one or more routed analog values.

51. The system of claim 45 , wherein:

the plurality of hardware components comprises one or more filters operable to filter a plurality of analog values, thereby generating a plurality of filtered analog values,

the system comprises a memory operable to store one or more filtered analog values of the plurality of filtered analog values, and

the behavioral model is operable to simulate the one or more filtered analog values for validation of the stored one or more filtered analog values.

52. The system of claim 45 , wherein:

the plurality of hardware components comprises a buffer operable to receive a plurality of digital markers from the plurality of software components,

the system comprises a memory operable to store one or more digital markers of the plurality of digital markers, and

the behavioral model is operable to simulate the one or more digital markers for validation of the stored one or more digital markers.

53. The system of claim 45 , wherein:

the plurality of hardware components comprises a variable delay operable to delay a plurality of digital markers, thereby generating a plurality of delayed digital markers,

the system comprises a memory operable to store one or more delayed digital markers of the plurality of delayed digital markers, and

the behavioral model is operable to simulate the one or more delayed digital markers for validation of the stored one or more delayed digital markers.

54. A method comprising:

selecting, via a hardware abstraction layer (HAL), a design for validation (DFV) test of a quantum controller;

orchestrating an interaction between a plurality of software components of the quantum controller and a plurality of hardware components of the quantum controller;

independently orchestrating a parallel interaction between the plurality of software components of the quantum controller and a behavioral model of the quantum controller;

setting the polarity of a plurality of digital markers, thereby generating a plurality of polarized digital markers;

storing one or more polarized digital markers of the plurality of polarized digital markers; and

simulating the one or more polarized digital markers for validation of the stored one or more polarized digital markers.

55. The method of claim 54 , wherein the method comprises:

extracting, via a design for validation (DFV) controller, data from the plurality of hardware components for validation.

56. The method of claim 54 , wherein the method comprises:

modifying analog values from the plurality of software components;

modifying digital markers from the plurality of software components; and

sending the modified analog values to a plurality of digital-to-analog converters (DACs) in coordination with outputting the modified digital markers.

57. The method of claim 54 , wherein the method comprises:

buffering a plurality of analog values from the plurality of software components;

storing one or more analog values of the plurality of analog values; and

simulating the one or more analog values for validation of the stored one or more analog values.

58. The method of claim 54 , wherein the method comprises:

modulating a plurality of analog values from the plurality of software components, thereby generating a plurality of modulated analog values;

storing one or more modulated analog values of the plurality of modulated analog values; and

simulating the one or more modulated analog values for validation of the stored one or more modulated analog values.

59. The method of claim 54 , wherein the method comprises:

routing a plurality of analog values to a digital to analog converter (DAC), thereby generating a plurality of routed analog values;

storing one or more routed analog values of the plurality of routed analog values; and

simulating the one or more routed analog values for validation of the stored one or more routed analog values.

60. The method of claim 54 , wherein the method comprises:

filtering a plurality of analog values, thereby generating a plurality of filtered analog values;

storing one or more filtered analog values of the plurality of filtered analog values; and

simulating the one or more filtered analog values for validation of the stored one or more filtered analog values.

61. The method of claim 54 , wherein the method comprises:

buffering a plurality of digital markers from the plurality of software components;

storing one or more digital markers of the plurality of digital markers; and

simulating the one or more digital markers for validation of the stored one or more digital markers.

62. The method of claim 54 , wherein the method comprises:

delaying a plurality of digital markers, thereby generating a plurality of delayed digital markers;

storing one or more delayed digital markers of the plurality of delayed digital markers; and

simulating the one or more delayed digital markers for validation of the stored one or more delayed digital markers.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 11, 2025

From: WEBER, ORI; SEMBIRA, TAMAR BEN HAIM; ELLA, LIOR; COHEN, YONATAN; OFEK, NISSIM; SIVAN, ITAMAR

To: Q.M TECHNOLOGIES LTD.

Reel/Frame 071983/0052 →

Continuity (1)

Related Publication 20230385672A1 · Nov 30, 2023

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