IP Library › Granted Patent US 12,555,022
Granted Patent B2
US 12,555,022 · App. 17/832,327 · Granted Feb 17, 2026

Systems and methods for embedding graphs using systolic algorithms

Inventors: Kelly T.R. Boothby (Vancouver, CA); Peter D. Spear (Burnaby, CA); Mani Ranjbar (Port Coquitlam, CA)
Assignee: D-WAVE SYSTEMS INC.
G06N10/80G06N10/60
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Quick Facts
Patent No.
US 12,555,022
App. No.
17/832,327
Granted
Feb 17, 2026
Kind
B2
Abstract

An accelerated version of a node-weighted path distance algorithm is implemented on a microprocessor coupled to a digital processor. The algorithm calculates an embedding of a source graph into a target graph (e.g., hardware graph of a quantum processor). The digital processor causes the microprocessor to send seeds to logic blocks with a corresponding node in the target graph contained in a working embedding of a node, compute a minimum distance to neighboring logic blocks from each seeded logic block, set the distance to neighboring logic blocks as the minimum distance plus the weight of the seeded logic block, increment the accumulator value by the weight of the seeded logic block, increment the accumulator value by the distance, determine the minimum distance logic block by computing the minimum accumulated value, compute distances to the minimum distance logic block; and read distances from all logic blocks into local memory.

Claims (48)

1 . A method for embedding a source graph S into a target graph T, the source and target graph each having a respective plurality of nodes and weighted edges, the method executed by a digital processor communicatively coupled at least one microprocessor, the at least one microprocessor having one logic block per each node of the target graph, the logic blocks communicatively coupled according to the edges of the target graph, the method comprising, for each neighbor v of a node u of the source graph S, wherein v is mapped to the target graph T via a working embedding E(v) that is non-empty:

causing the microprocessor to send seeds to logic blocks with a corresponding node in the target graph contained in E(v);

causing the microprocessor to compute a respective minimum distance N to neighboring logic blocks from each seeded logic block;

causing the microprocessor to set, for each seeded logic block, a respective distance D to neighboring logic blocks as the respective minimum distance N plus a respective weight of the seeded logic block;

causing the microprocessor to increment, for each seeded logic block, a respective accumulator value by a respective weight of the seeded logic block;

causing the microprocessor to increment, for each seeded logic block, the respective accumulator value by the respective distance D;

causing the microprocessor to determine a minimum distance logic block by computing a minimum accumulated value A′ over the respective accumulator values of the seeded logic blocks;

causing the microprocessor to compute distances D min , for each logic block, to the minimum distance logic block; and

causing the microprocessor to read distances D min from all logic blocks into local memory,

wherein causing the microprocessor to compute distances D min includes causing the microprocessor to compute a respective minimum distance N to the minimum distance logic block from each logic block; and causing the microprocessor to set, for each logic block, a respective distance D min to the minimum distance logic block as the respective minimum distance N plus a respective weight of the logic block.

2 . The method of claim 1 , further comprising causing the microprocessor to perform at least one of: sending edge weights to the logic blocks, sending edge masks to the logic blocks, and sending tie-break values to the logic blocks, before causing the microprocessor to send seeds to logic blocks.

3 . The method of claim 2 , further comprising causing the microprocessor to set the respective accumulator value to zero for all logic blocks, after causing the microprocessor to perform at least one of: sending edge weights to the logic blocks, sending edge masks to the logic blocks, and sending tie-break values to the logic blocks.

4 . The method of claim 1 , wherein causing the microprocessor to send seeds to logic blocks with a corresponding node in the target graph contained in E(v), causing the microprocessor to compute a respective minimum distance N to neighboring logic blocks from each seeded logic block, causing the microprocessor to set, for each seeded logic block, a respective distance D to neighboring logic blocks as the respective minimum distance N plus a respective weight of the seeded logic block, causing the microprocessor to increment, for each seeded logic block, a respective accumulator value by a respective weight of the seeded logic block, causing the microprocessor to increment, for each seeded logic block, the respective accumulator value by the respective distance D, causing the microprocessor to determine a minimum distance logic block by computing a minimum accumulated value A′ over the respective accumulator values of the seeded logic blocks, causing the microprocessor to compute distances D min , for each logic block, to the minimum distance logic block, and causing the microprocessor to read distances D min from all logic blocks into local memory include causing a field-programmable gate arrays (FPGA) to send seeds to logic blocks with a corresponding node in the target graph contained in E(v), causing the FPGA to compute a respective minimum distance N to neighboring logic blocks from each seeded logic block, causing the FPGA to set, for each seeded logic block, a respective distance D to neighboring logic blocks as the respective minimum distance N plus a respective weight of the seeded logic block, causing the FPGA to increment, for each seeded logic block, a respective accumulator value by a respective weight of the seeded logic block, causing the FPGA to increment, for each seeded logic block, the respective accumulator value by the respective distance D, causing the FPGA to determine a minimum distance logic block by computing a minimum accumulated value A′ over the respective accumulator values of the seeded logic blocks, causing the FPGA to compute distances D min , for each logic block, to the minimum distance logic block, and causing the FPGA to read distances D min from all logic blocks into local memory.

5 . The method of claim 1 , wherein causing the microprocessor to send seeds to logic blocks with a corresponding node in the target graph contained in E(v), causing the microprocessor to compute a respective minimum distance N to neighboring logic blocks from each seeded logic block, causing the microprocessor to set, for each seeded logic block, a respective distance D to neighboring logic blocks as the respective minimum distance N plus a respective weight of the seeded logic block, causing the microprocessor to increment, for each seeded logic block, a respective accumulator value by a respective weight of the seeded logic block, causing the microprocessor to increment, for each seeded logic block, the respective accumulator value by the respective distance D, causing the microprocessor to determine a minimum distance logic block by computing a minimum accumulated value A′ over the respective accumulator values of the seeded logic blocks, causing the microprocessor to compute distances D min , for each logic block, to the minimum distance logic block, and causing the microprocessor to read distances D min from all logic blocks into local memory include causing an application-specific integrated circuit (ASIC) to send seeds to logic blocks with a corresponding node in the target graph contained in E(v), causing the ASIC to compute a respective minimum distance N to neighboring logic blocks from each seeded logic block, causing the ASIC to set, for each seeded logic block, a respective distance D to neighboring logic blocks as the respective minimum distance N plus a respective weight of the seeded logic block, causing the ASIC to increment, for each seeded logic block, a respective accumulator value by a respective weight of the seeded logic block, causing the ASIC to increment, for each seeded logic block, the respective accumulator value by the respective distance D, causing the ASIC to determine a minimum distance logic block by computing a minimum accumulated value A′ over the respective accumulator values of the seeded logic blocks, causing the ASIC to compute distances D min , for each logic block, to the minimum distance logic block, and causing the ASIC to read distances D min from all logic blocks into local memory.

6 . The method of claim 1 , wherein causing the microprocessor to send seeds to all logic blocks with a corresponding node in the target graph contained in E(v), and causing the microprocessor to compute a respective minimum distance N to neighboring logic blocks include causing the microprocessor to send seeds to all logic blocks with a corresponding node contained in E(v) in a hardware graph of a quantum processor; and causing the microprocessor to compute a respective minimum distance N to neighboring logic blocks, wherein neighboring logic blocks are communicatively coupled according to the edges of the hardware graph of the quantum processor.

7 . The method of claim 1 , further comprising the digital processor using distances D min to determine an embedding of the source graph to a hardware graph of a quantum processor; and programming the quantum processor to embed the source graph into the hardware graph.

8 . The method of claim 1 , wherein causing the microprocessor to determine a minimum distance logic block by computing a minimum accumulated value A′ over the respective accumulator values includes causing the microprocessor to use unique tie-break values of each seeded logic block to determine a minimum distance logic block, should more than one logic block have minimum accumulated value A′.

9 . The method of claim 1 , wherein causing the microprocessor to set, for each seeded logic block, a respective distance D to neighboring logic blocks as the respective minimum distance N plus a respective weight of the seeded logic block includes, for each seeded logic block:

broadcasting a i th most significant bit of the distance D to a first neighbor, wherein i is the most significant bit of D;

determining whether all bits of D have been broadcasted;

in response to determining that all bits of D have been broadcasted, until all bits of D have been broadcasted, storing the i th most significant bit of the distance D in an array Z;

computing a minimum entry of Z;

setting a value of the minimum distance N to twice the value of the minimum distance N plus the minimum entry of Z; and

broadcasting a (i+1) th most significant bit of the distance D to the first neighbor.

10 . A hybrid computing system for embedding a source graph S into a target graph T, the source graph S and target graph T each having a respective plurality of nodes and weighted edges, the hybrid computing system comprising at least one digital processor, the at least one digital processor communicatively coupled at least one microprocessor, wherein the at least one microprocessor has one logic block per each node of the target graph and logic blocks are communicatively coupled according to the edges of the target graph, the digital processor operable to, for each neighbor v of a node u of the source graph S, wherein v is mapped to the target graph T via a working embedding E(v) that is non-empty:

cause the microprocessor to send seeds to logic blocks with a corresponding node in the target graph contained in E(v);

cause the microprocessor to compute a respective minimum distance N to neighboring logic blocks from each seeded logic block;

cause the microprocessor to set, for each seeded logic block, a respective distance D to neighboring logic blocks as the respective minimum distance N plus a respective weight of the seeded logic block;

cause the microprocessor to increment, for each seeded logic block, a respective accumulator value by a respective weight of the seeded logic block;

cause the microprocessor to increment, for each seeded logic block, the respective accumulator value by the respective distance D;

cause the microprocessor to determine a minimum distance logic block by computing a minimum accumulated value A′ over the respective accumulator values of the seeded logic blocks;

cause the microprocessor to compute a respective minimum distance N to the minimum distance logic block from each logic block;

cause the microprocessor to set, for each logic block, a respective distance D min to the minimum distance logic block as the respective minimum distance N plus a respective weight of the seeded logic block; and

cause the microprocessor to read distances D min from all logic blocks into local memory.

11 . The hybrid computing system of claim 10 , wherein the at least one digital processor is communicatively coupled to a quantum processor, the quantum processor having a plurality of qubits communicatively coupled according to a hardware graph, and wherein the target graph T corresponds to the hardware graph.

12 . The hybrid computing system of claim 11 , wherein neighboring logic blocks in the at least one microprocessor are communicatively coupled according to the edges of the hardware graph of the quantum processor.

13 . The hybrid computing system of claim 12 , wherein the at least one digital processor is further operable to: use distances D min to determine an embedding of the source graph to the hardware graph; and program the quantum processor to embed the source graph into the hardware graph.

14 . The hybrid computing system of claim 10 , wherein the at least one microprocessor is selected from a group consisting of: a programmable gate arrays (FPGA), and an application-specific integrated circuit (ASIC).

15 . The hybrid computing system of claim 10 , wherein the digital processor is further operable to cause the microprocessor to perform at least one of: sending edge weights to the logic blocks, sending edge masks to the logic blocks, and sending tie-break values to the logic blocks, before causing the microprocessor to send seeds to logic blocks.

16 . The hybrid computing system of claim 15 wherein the digital processor is further operable to cause the microprocessor to set the respective accumulator value to zero for all logic blocks, after causing the microprocessor to perform at least one of: sending edge weights to the logic blocks, sending edge masks to the logic blocks, and sending tie-break values to the logic blocks.

17 . The hybrid computing system of claim 10 , wherein the digital processor is operable to cause the microprocessor to use unique tie-break values of each seeded logic block to determine a minimum distance logic block, should more than one logic block have minimum accumulated value A′.

18 . The hybrid computing system of claim 10 , wherein the digital processor is operable to, for each seeded logic block:

broadcast a i th most significant bit of the distance D to a first neighbor, wherein i is the most significant bit of D;

determine whether all bits of D have been broadcasted;

in response to determining that all bits of D have been broadcasted, until all bits of D have been broadcasted, store the i th most significant bit of the distance D in an array Z;

compute a minimum entry of Z;

set a value of the minimum distance N to twice the value of the minimum distance N plus the minimum entry of Z; and

broadcast an (i+1) th most significant bit of the distance D to the first neighbor.

Assignments (2)
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2025
From: PSPIB UNITAS INVESTMENTS II INC.
To: D-WAVE SYSTEMS INC.; 1372934 B.C. LTD.
Reel/Frame 070470/0098 →
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Apr 14, 2023
From: D-WAVE SYSTEMS INC.; 1372934 B.C. LTD.
To: PSPIB UNITAS INVESTMENTS II INC., AS COLLATERAL AGENT
Reel/Frame 063340/0888 →
Continuity (2)
Provisional Application 63208122 · Jun 8, 2021
Related Publication 20220391744A1 · Dec 8, 2022
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