Method, device, and circuit for high-speed memories

1. A memory device, comprising:

a plurality of memory cells arranged in an array;

an input/output (I/O) interface, connected to the plurality of memory cells to output data signal from each memory cell; and

a control circuit, comprising:

a first clock generator configured to generate a first clock signal and a second clock signal according to an input clock signal and a chip enable (CE) signal, and provide the first clock signal to the plurality of memory cells; and

a second clock generator distinct from the first clock generator, and configured to generate a third clock signal according to the input clock signal and provide the first clock generator with a design for testability (DFT) enable (DFTEN) signal;

wherein the control circuit generates an output clock signal according to the second clock signal or the third clock signal.

2. The memory device of claim 1 , wherein the control circuit performs a logic OR operation on the second clock signal and the third clock signal to generate the output clock signal.

3. The memory device of claim 1 , wherein the DFTEN signal is generated by performing a logic OR operation on a scan enable (SE) signal and a DFT bypass (DFTBYP) signal.

4. The memory device of claim 1 , wherein in response to the DFTEN signal being in a high logic state, the memory device is in a DFT mode, and the output clock signal generated by the control circuit follows the third clock signal, wherein in response to the DFTEN signal being in a low logic state, the output clock signal generated by the control circuit follows the second clock signal.

5. The memory device of claim 1 , wherein the control circuit performs a logic NOR on the second clock signal and the third clock signal to generate a fourth clock signal, and the fourth clock signal passes through an inverter to generate the output clock signal.

6. The memory device of claim 1 , wherein the second clock signal passes through a first inverter to generate a fourth clock signal, the third clock signal passes through a second inverter to generate a fifth clock signal, and the control circuit performs a logic NAND on the fourth clock signal and the fifth clock signal to generate the output clock signal.

7. The memory device of claim 1 , wherein the second clock generator provides a buffered version of the DFTEN signal to the first clock generator.

8. The memory device of claim 1 , wherein the second clock generator generates the third clock signal according to the input clock signal, the DFTEN signal, and an initialization (INIT) signal.

9. The memory device of claim 1 , wherein a distance between the control circuit and each of the plurality of memory cells and the I/O interface is greater than ten microns.

10. A control circuit, comprising:

a first clock generator to generate a mission mode clock (MDCK) signal according to an input clock signal and a chip enable (CE) signal; and

a second clock generator to generate a design for testability (DFT) mode clock (DDCK) signal according to the input clock signal and provide the first clock generator with a DFT enable (DFTEN) signal; and

a logic gate to generate an output clock signal according to the MDCK signal or the DDCK signal.

11. The control circuit of claim 10 , wherein the control circuit performs a logic OR operation on the MDCK signal and the DDCK signal to generate the output clock signal.

12. The control circuit of claim 10 , wherein the DFTEN signal is generated by performing a logic OR operation on a scan enable (SE) signal and a DFT bypass (DFTBYP) signal.

13. The control circuit of claim 10 , wherein in response to the DFTEN signal being in a high logic state, the output clock signal generated by the logic gate is according to the DDCK signal, wherein in response to the DFTEN signal being in a low logic state, the output clock signal generated by the logic gate is according to the MDCK signal.

14. The control circuit of claim 10 , wherein the control circuit performs a logic NOR on the MDCK signal and the DDCK signal to generate a first clock signal, and the first clock signal passes through an inverter to generate the output clock signal.

15. The control circuit of claim 10 , wherein the MDCK signal passes through a first inverter to generate a first clock signal, the DDCK signal passes through a second inverter to generate a second clock signal, and the control circuit performs a logic NAND on the first clock signal and the second clock signal to generate the output clock signal.

16. The control circuit of claim 10 , wherein the second clock generator provides a buffered DFTEN signal to the first clock generator.

17. The control circuit of claim 10 , wherein the second clock generator generates the DDCK signal according to the input clock signal, the DFTEN signal, and an initialization (INIT) signal.

18. The control circuit of claim 10 , wherein the first clock generator generates a global clock (GCK) signal according to the input clock signal and the chip enable (CE) signal, and provide the GCK signal to a plurality of memory cells.

19. A control circuit, comprising:

a first clock generator to generate a mission mode clock (MDCK) signal according to an input clock signal and a chip enable (CE) signal; and

a second clock generator to generate a design for testability (DFT) mode clock (DDCK) signal according to the input clock signal and provide the first clock generator with a DFT enable (DFTEN) signal; and

a logic gate to generate an output clock signal according to the MDCK signal or the DDCK signal;

wherein in response to the DFTEN signal being in a high logic state, the output clock signal follows the DDCK signal, and wherein in response to the DFTEN signal being in a low logic state, the output clock signal follows the MDCK signal.

20. The control circuit of claim 19 , wherein the control circuit performs a logic OR operation on the MDCK signal and the DDCK signal to generate the output clock signal.