IP Library Granted Patent US 12,387,021
Granted Patent B2
US 12,387,021 · App. 17/834,815 · Granted Aug 12, 2025

Using information flow for security aware design and analysis

Inventors: Jason K. Oberg (Redwood City, CA); Alric Althoff (San Jose, CA); Andreas Kuehlmann (Kensington, CA)
Assignee: Cycuity, Inc.
G06F30/327G06F21/577G06F30/33G06F30/34G06F30/3308G06F30/367G06F30/398
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Quick Facts
Patent No.
US 12,387,021
App. No.
17/834,815
Granted
Aug 12, 2025
Kind
B2
Abstract

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for performing information flow analysis on hardware designs to identify vulnerabilities. One of the methods includes generating input signals and feeding the generated input signals into the modified hardware design to generate a plurality of information flow signals, wherein the information flow signals each associate a respective input signal with a location in the modified hardware design to which the input signal was able to reach through logic circuitry of the modified hardware design. The generated information flow signals are evaluated according to one or more security criteria to generate security results. One or more security related applications are performed to generate information representing aspects of the design that are vulnerable to insecure behavior.

Claims (44)

1. A computer-implemented method comprising:

receiving an initial hardware design;

generating a modified hardware design including modifying the initial hardware design to insert information flow logic; and

generating input signals and feeding the generated input signals into the modified hardware design to generate a plurality of information flow signals, wherein the information flow signals each associate a respective input signal with a location in the modified hardware design to which the input signal was able to reach through logic circuitry of the modified hardware design;

evaluating the generated information flow signals according to one or more security criteria to generate security results; and

performing one or more security related applications based on the generated security results to generate information representing aspects of the design that are vulnerable to insecure behavior.

2. The method of claim 1 , wherein generating the input signals comprises performing a concrete simulation that specifies pregenerated bit patterns for the input signals.

3. The method of claim 1 , wherein generating the input signals comprises connecting the modified hardware design to an operating environment and receiving input signals generated from the operating environment.

4. The method of claim 1 , wherein evaluating the generated information flow signals according to the one or more security criteria comprises:

determining that a critical design asset flowed to a location in the design specified by the one or more security criteria.

5. The method of claim 1 , wherein evaluating the generated information flow signals according to the one or more security criteria comprises:

determining that attacker controlled data flowed to a location in the design specified by the one or more security criteria.

6. The method of claim 1 , wherein evaluating the generated information flow signals according to the one or more security criteria comprises:

storing the information flow signals in an information flow signal database; and

issuing one or more queries to the database, the one or more queries representing the one or more security criteria.

7. The method of claim 6 , further comprising ranking or filtering results from the database according to one or more security metrics.

8. The method of claim 6 , further comprising generating a user interface presentation that presents result from the database.

9. The method of claim 6 , wherein the one or more queries generate results representing a confidentiality vulnerability or an integrity vulnerability.

10. The method of claim 6 , wherein the one or more queries generate results representing regions of the design that require physical alterations to mitigate the presence of vulnerabilities after manufacturing.

11. A system comprising:

one or more computers and one or more storage devices storing instructions that are operable, when executed by the one or more computers, to cause the one or more computers to perform operations comprising:

receiving an initial hardware design;

generating a modified hardware design including modifying the initial hardware design to insert information flow logic; and

generating input signals and feeding the generated input signals into the modified hardware design to generate a plurality of information flow signals, wherein the information flow signals each associate a respective input signal with a location in the modified hardware design to which the input signal was able to reach through logic circuitry of the modified hardware design;

evaluating the generated information flow signals according to one or more security criteria to generate security results; and

performing one or more security related applications based on the generated security results to generate information representing aspects of the design that are vulnerable to insecure behavior.

12. The system of claim 11 , wherein generating the input signals comprises performing a concrete simulation that specifies pregenerated bit patterns for the input signals.

13. The system of claim 11 , wherein generating the input signals comprises connecting the modified hardware design to an operating environment and receiving input signals generated from the operating environment.

14. The system of claim 11 , wherein evaluating the generated information flow signals according to the one or more security criteria comprises:

determining that a critical design asset flowed to a location in the design specified by the one or more security criteria.

15. The system of claim 11 , wherein evaluating the generated information flow signals according to the one or more security criteria comprises:

determining that attacker controlled data flowed to a location in the design specified by the one or more security criteria.

16. The system of claim 11 , wherein evaluating the generated information flow signals according to the one or more security criteria comprises:

storing the information flow signals in an information flow signal database; and

issuing one or more queries to the database, the one or more queries representing the one or more security criteria.

17. The system of claim 16 , wherein the operations further comprise ranking or filtering results from the database according to one or more security metrics.

18. The system of claim 16 , wherein the operations further comprise generating a user interface presentation that presents result from the database.

19. The system of claim 16 , wherein the one or more queries generate results representing a confidentiality vulnerability or an integrity vulnerability.

20. One or more non-transitory computer storage media encoded with computer program instructions that when executed by one or more computers cause the one or more computers to perform operations comprising:

receiving an initial hardware design;

generating a modified hardware design including modifying the initial hardware design to insert information flow logic; and

generating input signals and feeding the generated input signals into the modified hardware design to generate a plurality of information flow signals, wherein the information flow signals each associate a respective input signal with a location in the modified hardware design to which the input signal was able to reach through logic circuitry of the modified hardware design;

evaluating the generated information flow signals according to one or more security criteria to generate security results; and

performing one or more security related applications based on the generated security results to generate information representing aspects of the design that are vulnerable to insecure behavior.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 2, 2026
From: CYCUITY, INC.
To: ARTERIS, INC.
Reel/Frame 074830/0617 →
MERGER Recorded Apr 9, 2026
From: ARTERIS, INC.; CABERNET MERGER SUB I, INC.; ARTERIS SECURITY, LLC
To: ARTERIS, INC.
Reel/Frame 074318/0437 →
CHANGE OF NAME Recorded Sep 27, 2023
From: TORTUGA LOGIC INC.
To: CYCUITY, INC.
Reel/Frame 065080/0635 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 19, 2022
From: OBERG, JASON K.; ALTHOFF, ALRIC; KUEHLMANN, ANDREAS
To: TORTUGA LOGIC INC.
Reel/Frame 060540/0356 →
Continuity (1)
Related Publication 20230394207A1 · Dec 7, 2023
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