Wire-based metallization for solar cells
Approaches for fabricating wire-based metallization for solar cells, and the resulting solar cells, are described. In an example, a solar cell includes a substrate having a back surface and an opposing light-receiving surface. A plurality of alternating N-type and P-type semiconductor regions is disposed in or above the back surface of the substrate. A conductive contact structure is disposed on the plurality of alternating N-type and P-type semiconductor regions. The conductive contact structure includes a plurality of metal wires. Each metal wire of the plurality of metal wires is parallel along a first direction to form a one-dimensional layout of a metallization layer for the solar cell.
1. A method of fabricating a solar cell, the method comprising:
forming a plurality of alternating N-type and P-type semiconductor regions in or above the back surface of a substrate, the substrate having the back surface and an opposing light-receiving surface, wherein each of the plurality of alternating N-type and P-type semiconductor regions is along a first direction;
forming a conductive contact structure on the plurality of alternating N-type and P-type semiconductor regions, the conductive contact structure comprising a plurality of metal wires, wherein each metal wire of the plurality of metal wires is parallel along a second direction to form a one-dimensional layout of a metallization layer for the solar cell, the second direction orthogonal to the first direction, and wherein each metal wire of the plurality of metal wires is continuously undulating between and extending beyond two bonding points coupling the metal wire to the plurality of alternating N-type and P-type semiconductor regions; and
forming a plurality of insulating wires, wherein each insulating wire of the plurality of insulating wires is parallel along the first direction, wherein each insulating wire of the plurality of insulating wires is vertically over and parallel with a corresponding one of the plurality of alternating N-type and P-type semiconductor regions, wherein each of the insulating wires is continuous over the corresponding one of the plurality of alternating N-type and P-type semiconductor regions, and wherein each of the insulating wires has a width in the second direction less than a width of the corresponding one of the plurality of alternating N-type and P-type semiconductor regions in the second direction.
2. The method of claim 1 , wherein each metal wire of the plurality of metal wires is undulating in a plane parallel with the back surface of the substrate.
3. The method of claim 1 , wherein each metal wire of the plurality of metal wires is undulating in a plane normal to the back surface of the substrate.
4. The method of claim 1 , wherein each metal wire of the plurality of metal wires comprises a stress relief feature.
5. The method of claim 1 , wherein each insulating wire of the plurality of insulating wires is woven through the plurality of metal wires.
6. The method of claim 5 , wherein the plurality of insulating wires provides structural integrity for the plurality of metal wires.
7. The method of claim 1 , wherein the conductive contact structure further comprises a metal seed layer between the plurality of alternating N-type and P-type semiconductor regions and the plurality of metal wires.
8. The method of claim 1 , wherein the substrate is a monocrystalline silicon substrate, and wherein the plurality of alternating N-type and P-type semiconductor regions is a plurality of N-type and P-type diffusion regions formed in the silicon substrate.
9. The method of claim 1 , wherein plurality of alternating N-type and P-type semiconductor regions is a plurality of N-type and P-type polycrystalline silicon regions formed above the back surface of the substrate.
10. A method of fabricating a photovoltaic assembly, the method comprising:
providing a plurality of substrates, each substrate having a back surface and an opposing light-receiving surface;
forming a plurality of alternating N-type and P-type semiconductor regions in or above the back surface of each of the plurality of substrates, wherein each of the plurality of alternating N-type and P-type semiconductor regions is along a first direction;
forming a conductive contact structure on the plurality of alternating N-type and P-type semiconductor regions of each of the substrates, the conductive contact structure comprising a plurality of metal wires, wherein each metal wire of the plurality of metal wires is parallel along a second direction to form a one-dimensional layout of a metallization layer for each of the substrates, the second direction orthogonal to the first direction, wherein one or more wires of the plurality of metal wires is common to two or more of the plurality of substrates, and wherein each metal wire of the plurality of metal wires is continuously undulating between and extending beyond two bonding points coupling the metal wire to the plurality of alternating N-type and P-type semiconductor regions; and
forming a plurality of insulating wires, wherein each insulating wire of the plurality of insulating wires is parallel along the first direction, wherein each insulating wire of the plurality of insulating wires is vertically over and parallel with a corresponding one of the plurality of alternating N-type and P-type semiconductor regions, wherein each of the insulating wires is continuous over the corresponding one of the plurality of alternating N-type and P-type semiconductor regions, and wherein each of the insulating wires has a width in the second direction less than a width of the corresponding one of the plurality of alternating N-type and P-type semiconductor regions in the second direction.
11. The method of claim 10 , wherein each metal wire of the plurality of metal wires comprises a stress relief feature.
12. The method of claim 10 , wherein each insulating wire of the plurality of insulating wires is woven through the plurality of metal wires, and wherein the plurality of insulating wires provides structural integrity for the plurality of metal wires.
13. The method of claim 10 , wherein the conductive contact structure further comprises a metal seed layer between the plurality of alternating N-type and P-type semiconductor regions of each substrate and the plurality of metal wires.