Method and device for timing and power adjustment in wireless communication
The present disclosure provides a method and device in nodes used for wireless communications. A first node transmits a first signal and a second signal, and the first signal and the second signal are both used for initiating a random access; and a target counter is used for counting of a random access; a count value of the target counter when transmitting the first signal is a first count value, and a count value of the target counter when transmitting the second signal is a second count value; a first timing offset value is used to determine a timing for transmitting the first signal. The application establishes a connection between a timing offset value and a number of transmission times of a random access channel to optimize the transmission scheme of the random access channel, thus improving the system performance.
1 . A first node for wireless communications, the first node comprising:
a transceiver; and
a processor, wherein the transceiver and the processor are configured to:
estimate a first timing offset value comprising a first timing advance of an uplink transmission from the first node to a second node,
determine, based on the first timing advance, a first timing for transmitting a first signal,
initiating a random access by transmitting the first signal at the first timing, wherein a target counter is used for counting in the random access initiated by the first node, and wherein a count value of the target counter is a positive integer, and wherein a count value of the target counter when transmitting the first signal is a first count value, and wherein the random access initiated by the first signal is unsuccessful,
estimate a second timing offset value comprising a second timing advance of the uplink transmission from the first node to the second node,
determine, based on the second timing advance, a second timing for transmitting a second signal,
initiating the random access by transmitting the second signal at the second timing, wherein the count value of the target counter when transmitting the second signal is a second count value,
wherein a size relation between the first count value and the second count value is based on whether the first timing offset value is equal to the second timing offset.
2 . The first node according to claim 1 , wherein when the first timing offset value is equal to the second timing offset value, the second count value is equal to the first count value plus 1;
and wherein when the first timing offset value is not equal to the second timing offset value, the second count value is not greater than the first count value.
3 . The first node according to claim 1 , wherein a format adopted by the first signal is related to the first timing offset value, and a format adopted by the second signal is related to the second timing offset value; and
wherein the format adopted by the first signal comprises at least one of a length of a sequence generating the first signal, a length of a cyclic prefix comprised in the first signal, or a blank length comprised in time-domain resources occupied by the first signal; and
wherein the format adopted by the second signal comprises at least one of a length of a sequence generating the second signal, a length of a cyclic prefix comprised in the second signal, or a blank length comprised in time-domain resources occupied by the second signal.
4 . The first node according to claim 1 , wherein the processor and the transceiver are further configured to:
receive first information, and
determine, based on the first information, a first target power value and a first step-size,
wherein when the first count value is greater than 1, the first target power value, the first step-size and the first count value are used together to determine a transmit power value of the first signal, and
wherein when the first count value is equal to 1, only the first target power value among the first target power value, the first step-size and the first count value is used to determine a transmit power value of the first signal.
5 . The first node according to claim 4 , wherein when the first timing offset value is equal to the second timing offset value, the first target power value, the first step-size and the second count value are used together to determine a transmit power value of the second signal.
6 . The first node according to claim 4 , wherein the processor and the transceiver are further configured to:
receive second information, and
determine a second step-size based on the second information,
wherein when the first timing offset value is not equal to the second timing offset value and the second count value is greater than 1, the first target power value, the second step-size and the second count value are used together to determine a transmit power value of the second signal, and
wherein when the first timing offset value is not equal to the second timing offset value and the second count value is equal to 1, only the first target power value among the first target power value, the second step-size and the second count value is used to determine a transmit power value of the second signal.
7 . The first node according to claim 1 , wherein the processor and the transceiver are further configured to:
receive a third signal, and
determine a reference timing based on the third signal,
wherein a timing offset between the first timing and the reference timing is equal to the first timing offset value, and
wherein the timing offset between the second timing and the reference timing is equal to the second timing offset value.
8 . The first node according to claim 1 , wherein a capability of the first node is used to determine the first timing offset value.
9 . The first node according to claim 1 , wherein the processor and the transceiver are further configured to:
receive third information, and
when the first timing offset value is not equal to the second timing offset value, the second count value is equal to 1, determine an upper limit of the first count value based on the third information.
10 . The first node according to claim 1 , wherein the first timing offset value is not equal to 0, and the first timing offset value is related to at least one of:
a type of the second node,
a height of the second node, or
position information of the first node.
11 . The first node according to claim 1 , wherein the second timing offset value is not equal to 0, and the second timing offset value is related to at least one of:
a type of the second node,
a height of the second node, or
position information of the first node.
12 . The first node according to claim 1 , wherein when the first timing offset value is not equal to the second timing offset value, the second count value is equal to 1, and
wherein when the first timing offset value is equal to the second timing offset value, the first count value is equal M, and the second count value is equal to M+1, M being a positive integer.
13 . The first node according to claim 1 , wherein a format adopted by the first signal is a first format, the first format is a format in a first format set, the first format set comprises one or a plurality of formats, and the first node generates the first signal by adopting the first format in the first format set when transmitting the first signal with the first timing offset value, and
wherein a format adopted by the second signal is a second format, the second format is a format in a second format set, the second format set comprises one or a plurality of formats, and the first node generates the second signal by adopting the second format in the second format set when transmitting the second signal with the second timing offset value.
14 . The first node according to claim 13 , wherein the first format and the second format respectively correspond to different generation sequence lengths, or
wherein the first format and the second format respectively correspond to different cyclic prefix lengths, or
wherein the first format and the second format respectively occupy different blank lengths.
15 . A second node for wireless communications, the second node comprising:
a transceiver; and
a processor, wherein the transceiver and the processor are configured to:
detect a first signal used to initiate a random access, wherein a target counter is used for counting in the random access initiated by a transmitter of the first signal, and wherein a count value of the target counter is a positive integer, and wherein a count value of the target counter when transmitting the first signal is a first count value, and wherein the random access initiated by the first signal is unsuccessful, and
detect a second signal used to initiate the random access, wherein the count value of the target counter when transmitting the second signal is a second count value, and
wherein a first timing offset value is used to determine a first timing for transmitting the first signal, and a second timing offset value is used to determine a second timing for transmitting the second signal, and
wherein whether the first timing offset value is equal to the second timing offset value is used to determine a size relation between the first count value and the second count value.
16 . The second node according to claim 15 , wherein when the first timing offset value is equal to the second timing offset value, the second count value is equal to the first count value plus 1, and
wherein when the first timing offset value is not equal to the second timing offset value, the second count value is not greater than the first count value, and
wherein the first timing offset value comprises a timing advance of an uplink transmission from a first node to the second node estimated by the first node, and
wherein the second timing offset value comprises a timing advance of an uplink transmission from the first node to the second node estimated by the first node.
17 . The second node according to claim 15 , wherein a format adopted by the first signal is related to the first timing offset value, and a format adopted by the second signal is related to the second timing offset value, and
wherein the format adopted by the first signal comprises at least one of a length of a sequence generating the first signal, a length of a cyclic prefix comprised in the first signal, or a blank length comprised in time-domain resources occupied by the first signal, and
wherein the format adopted by the second signal comprises at least one of a length of a sequence generating the second signal, a length of a cyclic prefix comprised in the second signal, or a blank length comprised in time-domain resources occupied by the second signal.
18 . The second node according to claim 15 , wherein the processor and the transceiver are further configured to:
transmit first information used to determine a first target power value and a first step-size,
wherein when the first count value is greater than 1, the first target power value, the first step-size and the first count value are used together to determine a transmit power value of the first signal, and
wherein when the first count value is equal to 1, only the first target power value among the first target power value, the first step-size and the first count value is used to determine a transmit power value of the first signal.
19 . The second node according to claim 18 , wherein when the first timing offset value is equal to the second timing offset value, the first target power value, the first step-size and the second count value are used together to determine a transmit power value of the second signal.
20 . A method in a first node for wireless communications, comprising:
transmitting a first signal used to initiate a random access; and
transmitting a second signal used to initiate a the random access,
wherein a target counter is used for counting in the random access initiated by the first node, and a count value of the target counter is a positive integer, and
wherein a count value of the target counter when transmitting the first signal is a first count value, and the count value of the target counter when transmitting the second signal is a second count value, and
wherein a first timing offset value is used to determine a first timing for transmitting the first signal, and a second timing offset value is used to determine a second timing for transmitting the second signal, and
wherein whether the first timing offset value is equal to the second timing offset value is used to determine a size relation between the first count value and the second count value, and
wherein the random access initiated by the first signal is unsuccessful, and
wherein the first timing offset value comprises a timing advance of an uplink transmission from the first node to a second node estimated by the first node, and
wherein the second timing offset value comprises a timing advance of an uplink transmission from the first node to the second node estimated by the first node.