Architecting an integrated circuit or system using machine learning
Systems and methods for designing a chip configured to perform computing processes are provided. The described techniques include obtaining information associated with the chip and determining, using a trained machine learning model and the information associated with the chip, selections of one or more circuit building blocks to be included in the chip. The chip architecture may then be generated to be used in fabrication of the chip based on the selections of the one or more circuit building blocks.
1. A method for designing a chip configured to perform computing processes, the method comprising:
obtaining information associated with the chip including representative workloads to be implemented on the chip and target metrics associated with the chip;
determining, using a trained machine learning model and the information associated with the chip, selections of one or more circuit building blocks to be included in the chip by:
obtaining an output based on evaluating at least one cost function indicative of the target metrics associated with the chip when the representative workloads are applied to a first selection of the one or more circuit building blocks; and
updating the first selection of the one or more circuit building blocks to obtain a second selection of the one or more circuit building blocks based on the obtained output; and
generating a chip architecture to use in fabrication of the chip based on the second selection of the one or more circuit building blocks.
2. The method of claim 1 , wherein obtaining the information associated with the chip further comprises obtaining one or more of: representative datasets, circuit building blocks and parameters related to the circuit building blocks, and/or a parameter constraint.
3. The method of claim 2 , wherein the parameters related to the circuit building blocks comprise performance and/or cost information.
4. The method of claim 2 , wherein the parameter constraint comprises at least one of power, performance, and/or area constraints.
5. The method of claim 1 , wherein determining the selections of one or more circuit building blocks comprises determining selections of electronic circuit blocks and/or photonic circuit blocks.
6. The method of claim 5 , wherein determining selections of the electronic circuit blocks and/or the photonic circuit blocks comprises determining selections of one or more of: a memory block, a microcontroller block, a microprocessor block, a photonic tensor multiplier block, a multiply and accumulate (MAC) block, a scheduler block, a control flow and/or logic block, and/or a networks on chip (NoCs) block.
7. The method of claim 1 , further comprising obtaining the trained machine learning model by training a machine learning model, the training comprising using unsupervised learning.
8. The method of claim 7 , wherein using unsupervised learning comprises using reinforcement learning.
9. The method of claim 8 , wherein using reinforcement learning comprises:
obtaining an output from the machine learning model;
calculating a reward using a reward function and the output, the reward function being a function of power, latency, area, and/or throughput of the chip; and
determining new parameter values of the machine learning model based on the calculated reward.
10. The method of claim 1 , further comprising obtaining the trained machine learning model by training a machine learning model, the training comprising using supervised learning based on a set of chip architectures.
11. The method of claim 1 , further comprising determining, using the trained machine learning model, a physical arrangement of the one or more circuit building blocks on the chip.
12. The method of claim 1 , further comprising obtaining the trained machine learning model by training a machine learning model using backpropagation, the backpropagation comprising using stochastic gradient-based optimizers.
13. At least one non-transitory computer readable storage medium storing processor-executable instructions that, when executed by at least one processor, cause the at least one processor to perform a method for designing a chip configured to perform computing processes, the method comprising:
obtaining information associated with the chip including representative workloads to be implemented on the chip and target metrics associated with the chip;
determining, using a trained machine learning model and the information associated with the chip, selections of one or more circuit building blocks to be included in the chip by:
obtaining an output based on evaluating at least one cost function indicative of the target metrics associated with the chip when the representative workloads are applied to a first selection of the one or more circuit building blocks; and
updating the first selection of the one or more circuit building blocks to obtain a second selection of the one or more circuit building blocks based on the obtained output; and
generating a chip architecture to use in fabrication of the chip based on the second selection of the one or more circuit building blocks.
14. The at least one non-transitory computer readable storage medium of claim 13 , wherein obtaining the information associated with the chip further comprises obtaining one or more of: representative datasets, circuit building blocks and parameters related to the circuit building blocks, and/or a parameter constraint.
15. The at least one non-transitory computer readable storage medium of claim 13 , wherein determining the selections of one or more circuit building blocks comprises determining selections of electronic circuit blocks and/or photonic circuit blocks.
16. The at least one non-transitory computer readable storage medium of claim 15 , wherein determining selections of the electronic circuit blocks and/or the photonic circuit blocks comprises determining selections of one or more of: a memory block, a microcontroller block, a microprocessor block, a photonic tensor multiplier block, a multiply and accumulate (MAC) block, a scheduler block, a control flow and/or logic block, and/or a networks on chip (NoCs) block.
17. The at least one non-transitory computer readable storage medium of claim 13 , further comprising obtaining the trained machine learning model by training a machine learning model, the training comprising using unsupervised learning.
18. The at least one non-transitory computer readable storage medium of claim 13 , further comprising determining, using the trained machine learning model, a physical arrangement of the one or more circuit building blocks on the chip.
19. The at least one non-transitory computer readable storage medium of claim 13 , further comprising obtaining the trained machine learning model by training a machine learning model using backpropagation, the backpropagation comprising using stochastic gradient-based optimizers.
20. A system comprising:
at least one processor configured to perform a method for designing a chip configured to perform computing processes, the method comprising:
obtaining information associated with the chip including representative workloads to be implemented on the chip and target metrics associated with the chip;
determining, using a trained machine learning model and the information associated with the chip, selections of one or more circuit building blocks to be included in the chip by:
obtaining an output based on evaluating at least one cost function indicative of the target metrics associated with the chip when the representative workloads are applied to a first selection of the one or more circuit building blocks; and
updating the first selection of the one or more circuit building blocks to obtain a second selection of the one or more building blocks based on the obtained output; and
generating a chip architecture to use in fabrication of the chip based on the second selection of the one or more circuit building blocks.