Methods and system with dynamic ECC voltage and frequency
Apparatus and methods are disclosed, including using a memory controller to monitor at least one parameter related to power level of a host processor of a host device, and dynamically adjusting at least one of a clock frequency and a voltage level of an error-correcting code (ECC) subsystem of the memory controller based on the at least one parameter to control power usage of the host device.
1. A non-transitory computer readable medium comprising instructions thereon that, when executed by a memory controller, cause the memory controller to perform operations comprising:
monitoring at least one parameter related to processing speed of a host processor of a host device configured to communicate with the memory controller; and
adjusting a voltage level of an error-correcting code (ECC) subsystem of a memory controller based on the at least one parameter to control power usage of the host device.
2. The non-transitory computer readable medium of claim 1 , wherein the instructions further cause the memory controller to perform operations comprising:
saving a last setting of the voltage level of the ECC subsystem of the memory controller.
3. The non-transitory computer readable medium of claim 2 , wherein the instructions further cause the memory controller to perform operations comprising:
restoring the last setting when entering or exiting sleep mode for the memory controller.
4. A storage system comprising:
a memory array; and
a memory controller configured to communicate with a host processor of a host device, wherein the memory controller is programmed to perform operations including:
monitoring at least one parameter related to processing speed of a host processor of a host device configured to communicate with the memory controller; and
adjusting a voltage level of an error-correcting code (ECC) subsystem of a memory controller based on the at least one parameter to control power usage of the host device.
5. The storage system of claim 4 , wherein the memory controller is further programmed to perform operations including:
comparing the at least one parameter to a programmable threshold; and
adjusting the voltage level of the ECC subsystem based on a result of the comparison.
6. The storage system of claim 5 , wherein the programmable threshold includes a setting that is configured through a ROM setting.
7. The storage system of claim 5 , wherein the programmable threshold includes a setting that is configured through a bootstrap hardware select pin.
8. The storage system of claim 5 , wherein the programmable threshold includes a setting that is configured through a substrate wiring option.
9. The storage system of claim 5 , wherein the programmable threshold includes a setting that is configured through a fuse.
10. The storage system of claim 5 , the programmable threshold includes a setting that is configured through a metal mask.
11. The storage system of claim 5 , wherein the memory controller is further programmed to perform operations including:
adjusting a clock frequency the ECC subsystem based on the result of the comparison.
12. The storage system of claim 4 , wherein the memory controller is further programmed to perform operations comprising:
saving a last setting of the voltage level of the ECC subsystem of the memory controller; and
restoring the last setting when entering or exiting sleep mode for the storage system.
13. A method comprising:
monitoring, by a memory controller, at least one parameter related to processing speed of a host processor of a host device configured to communicate with the memory controller; and
adjusting, by the memory controller, a voltage level of an error-correcting code (ECC) subsystem of a memory controller based on the at least one parameter to control power usage of the host device.
14. The method of claim 13 , further comprising:
comparing, by the memory controller, the at least one parameter to a programmable threshold; and
adjusting, by the memory controller, the voltage level of the ECC subsystem based on a result of the comparison.
15. The method of claim 14 , further comprising:
adjusting, by the memory controller, a clock frequency of the ECC subsystem based on the result of the comparison.
16. The method of claim 15 , wherein adjusting the clock frequency of the ECC subsystem includes using glitch-less clocking to support dynamic frequency changes for the ECC subsystem.
17. The method of claim 15 , wherein adjusting the clock frequency of the ECC subsystem includes selecting a channel of the ECC subsystem having a per channel frequency system that supports different frequencies for operation of the ECC subsystem on different channels.
18. The method of claim 13 , wherein the ECC subsystem includes a per channel voltage system that supports different voltages for operation of the ECC subsystem on different channels.
19. The method of claim 13 , wherein the ECC subsystem includes a ECC generation logic and a ECC checking logic, and wherein the ECC generation logic is configured to operate at a different voltage level than the ECC checking logic.
20. The method of claim 13 , wherein the ECC subsystem includes a ECC generation logic and a ECC checking logic, and wherein the ECC generation logic is configured to operate at a different frequency level than the ECC checking logic.