Synchronizing concurrent tasks using interrupt deferral instructions
An example method may include responsive to receiving, by a processing device, an interrupt deferral instruction requesting that interrupts be deferred, disabling delivery of interrupts by the processing device, receiving one or more interrupt requests subsequent to disabling delivery of interrupts, and responsive to determining that a deferral termination criterion is satisfied, delivering one or more interrupts, wherein each of the one or more interrupts is specified by a respective one of the interrupt requests. The method may further include receiving a resume interrupt delivery instruction requesting that deferred and subsequent interrupts be delivered, wherein the deferral termination criterion is satisfied in response to receiving the resume interrupt delivery instruction. The method may further include, responsive to receiving the resume interrupt delivery instruction, enabling delivery of the one or more interrupts and subsequent interrupts by the processing device.
1. A method comprising:
responsive to receiving, by a processing device, an interrupt deferral instruction requesting that interrupts be deferred, disabling delivery of interrupts by the processing device;
receiving one or more interrupt requests subsequent to disabling delivery of interrupts; and
responsive to determining that a deferral termination criterion is satisfied, delivering one or more interrupts, wherein each of the one or more interrupts is specified by a respective one of the interrupt requests, and wherein the deferral termination criterion is satisfied if an execution time of an application since receiving the interrupt deferral instruction exceeds a predefined fraction of a scheduling quota associated with the application.
2. The method of claim 1 , further comprising:
receiving a resume interrupt delivery instruction requesting that deferred and subsequent interrupts be delivered, wherein the deferral termination criterion is satisfied in response to receiving the resume interrupt delivery instruction.
3. The method of claim 2 , further comprising:
responsive to receiving the resume interrupt delivery instruction, enabling delivery of the one or more interrupts and subsequent interrupts by the processing device.
4. The method of claim 2 , wherein the interrupt deferral instruction and the resume interrupt delivery instruction are called by program code executing in an unprivileged mode of the processing device.
5. The method of claim 1 , further comprising:
determining, in view of a numeric difference value that corresponds to an amount of time that has elapsed since receiving the interrupt deferral instruction, whether a timeout criterion is satisfied, wherein the deferral termination criterion is satisfied if the timeout criterion is satisfied.
6. The method of claim 5 , wherein the timeout criterion is satisfied if the numeric difference value exceeds a threshold timeout value.
7. The method of claim 5 , wherein the numeric difference value is determined in view of a current counter value and a threshold counter value, wherein the current counter value corresponds to an amount of time for which the application has been executing since receiving the interrupt deferral instruction, and wherein the threshold counter value is received from an operating system supervisor.
8. The method of claim 5 , wherein the numeric difference value is determined in view of a difference between a current time and a time at which interrupt delivery was disabled.
9. The method of claim 5 , wherein the numeric difference value corresponds to a number of instructions executed by the processing device since disabling delivery of interrupts.
10. The method of claim 1 , further comprising:
storing each of the one or more interrupt requests in a data structure, wherein delivering the one or more interrupts comprises retrieving the one or more interrupt requests from the data structure.
11. A non-transitory machine-readable storage medium storing instructions that cause a processing device to perform operations comprising:
responsive to receiving an interrupt deferral instruction requesting that interrupts be deferred, disabling delivery of interrupts by the processing device;
receiving one or more interrupt requests subsequent to disabling delivery of interrupts; and
responsive to determining that a deferral termination criterion is satisfied, delivering one or more interrupts, wherein each of the one or more interrupts is specified by a respective one of the interrupt requests, and wherein the deferral termination criterion is satisfied if an execution time of an application since receiving the interrupt deferral instruction exceeds a predefined fraction of a scheduling quota associated with the application.
12. The non-transitory machine-readable storage medium of claim 11 , the operations further comprising:
receiving a resume interrupt delivery instruction requesting that deferred and subsequent interrupts be delivered, wherein the deferral termination criterion is satisfied in response to receiving the resume interrupt delivery instruction.
13. The non-transitory machine-readable storage medium of claim 12 , the operations further comprising:
responsive to receiving the resume interrupt delivery instruction, enabling delivery of the one or more interrupts and subsequent interrupts by the processing device.
14. The non-transitory machine-readable storage medium of claim 12 , wherein the interrupt deferral instruction and the resume interrupt delivery instruction are called by program code executing in an unprivileged mode of the processing device.
15. The non-transitory machine-readable storage medium of claim 11 , the operations further comprising:
determining, in view of a numeric difference value that corresponds to an amount of time that has elapsed since receiving the interrupt deferral instruction, whether a timeout criterion is satisfied,
wherein the deferral termination criterion is satisfied if the timeout criterion is satisfied.
16. A system comprising:
a memory device; and
a processing device, operatively coupled to the memory device, to perform operations comprising:
responsive to receiving an interrupt deferral instruction requesting that interrupts be deferred, disabling delivery of interrupts by the processing device;
receiving one or more interrupt requests subsequent to disabling delivery of interrupts; and
responsive to determining that a deferral termination criterion is satisfied, delivering one or more interrupts, wherein each of the one or more interrupts is specified by a respective one of the interrupt requests, and wherein the deferral termination criterion is satisfied if an execution time of an application since receiving the interrupt deferral instruction exceeds a predefined fraction of a scheduling quota associated with the application.
17. The system of claim 16 , the operations further comprising:
receiving a resume interrupt delivery instruction requesting that deferred and subsequent interrupts be delivered, wherein the deferral termination criterion is satisfied in response to receiving the resume interrupt delivery instruction.
18. The system of claim 17 , the operations further comprising:
responsive to receiving the resume interrupt delivery instruction, enabling delivery of the one or more interrupts and subsequent interrupts by the processing device.
19. The system of claim 17 , wherein the interrupt deferral instruction and the resume interrupt delivery instruction are called by program code executing in an unprivileged mode of the processing device.
20. The method of claim 1 , wherein the interrupt deferral instruction is invoked by a first execution thread, the method further comprising:
accessing, by the first execution thread, a shared resource that is also accessible by a second execution thread.