Precision tuning of a page or word of non-volatile memory cells in an analog neural memory system
Numerous examples for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. In one example, an analog neural memory system comprises an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a word line terminal, a bit line terminal, and an erase gate terminal; a plurality of word lines, each word line coupled to word line terminals of a row of non-volatile memory cells; a plurality of bit lines, each bit line coupled to bit line terminals of a column of non-volatile memory cells; and a plurality of erase gate enable transistors, each erase gate enable transistor coupled to erase gate terminals of a word of non-volatile memory cells.
1. An analog neural memory system comprising:
an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a word line terminal, a bit line terminal, and an erase gate terminal;
a plurality of word lines, each word line coupled to word line terminals of a row of non-volatile memory cells;
a plurality of bit lines, each bit line coupled to bit line terminals of a column of non-volatile memory cells; and
a plurality of erase gate enable transistors, each erase gate enable transistor configured to apply a voltage to erase gate terminals of a word of non-volatile memory cells when turned on.
2. The system of claim 1 , further comprising:
a plurality of erase gate lines, each erase gate line coupled to an erase gate enable transistor.
3. An analog neural memory system comprising:
an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a word line terminal, a bit line terminal, and an erase gate terminal;
a plurality of word lines, each word line coupled to word line terminals of a row of non-volatile memory cells;
a plurality of bit lines, each bit line coupled to bit line terminals of a column of non-volatile memory cells; and
a plurality of erase gate enable transistors, each erase gate enable transistor coupled to erase gate terminals of a word of non-volatile memory cells;
wherein a word in a first row and a word in a second row adjacent to the first row share one source line.
4. The system of claim 1 , wherein each word includes one cell.
5. The system of claim 1 , wherein each word includes more than one cell.
6. An analog neural memory system comprising:
an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a word line terminal, a bit line terminal, and an erase gate terminal;
a plurality of word lines, each word line coupled to word line terminals of a row of non-volatile memory cells;
a plurality of bit lines, each bit line coupled to bit line terminals of a column of non-volatile memory cells; and
a plurality of erase gate enable transistors, each erase gate enable transistor configured to apply a voltage when turned on coupled to erase gate terminals of a page of non-volatile memory cells, the page comprising two words of non-volatile memory cells in adjacent rows.
7. The system of claim 6 , further comprising:
a plurality of erase gate lines, each erase gate line coupled to an erase gate enable transistor.
8. The system of claim 6 , wherein non-volatile memory cells forming a word can be programmed or erased concurrently by turning on an erase gate enable transistor coupled to a respective one of the plurality of erase gate lines.
9. The system of claim 7 , wherein the erase gate lines are orthogonal to control gate lines.