Semiconductor packages for alternate stacked memory and methods of manufacturing the same
A semiconductor package includes a silicon die including a first die surface coupled to a package substrate, a second die surface opposite to the first die surface, and at least one die sidewall orthogonal to the first die surface and the second die surface, and a mold layer including a first mold surface, a second mold surface opposite to the first mold surface, and at least one mold sidewall orthogonal to the first mold surface and the second mold surface, the at least one mold sidewall being disposed along the at least one die sidewall, and the mold layer further including a power conductive corridor extending from the first mold surface and coupled to the package substrate through the first mold surface. The semiconductor package further includes a first stacked device coupled to the first die surface and to the power conductive corridor through the first mold surface.
1 . A semiconductor package comprising:
a silicon die comprising a first die surface coupled to a package substrate, a second die surface opposite to the first die surface, and at least one die sidewall orthogonal to the first die surface and the second die surface;
a mold layer comprising a first mold surface, a second mold surface opposite to the first mold surface, and at least one mold sidewall orthogonal to the first mold surface and the second mold surface, the at least one mold sidewall being disposed along the at least one die sidewall, and the mold layer further comprising a power conductive corridor extending from the first mold surface and coupled to the package substrate through the first mold surface;
a first stacked device coupled to the first die surface and to the power conductive corridor through the first mold surface; and
a second stacked device coupled to the second die surface and to the power conductive corridor through the second mold surface.
2 . The semiconductor package of claim 1 , wherein the mold layer further comprises a power conductive plane extending from the power conductive corridor in parallel to the first mold surface and the second mold surface.
3 . The semiconductor package of claim 2 , wherein the mold layer further comprises:
a first power conductive via extending from the power conductive plane through the first mold surface, and coupled to the first stacked device; and
a second power conductive via extending from the power conductive plane through the second mold surface, and coupled to the second stacked device.
4 . The semiconductor package of claim 3 , wherein the second power conductive via is integrally formed with the first power conductive via.
5 . The semiconductor package of claim 3 , wherein the second power conductive via is horizontally offset from the first power conductive via.
6 . The semiconductor package of claim 3 , wherein the power conductive corridor, the power conductive plane, the first power conductive via and the second power conductive via are connected to a power supply voltage.
7 . The semiconductor package of claim 3 , wherein the mold layer further comprises:
a ground conductive corridor extending from the first mold surface and coupled to the package substrate through the first mold surface;
a ground conductive plane extending from the ground conductive corridor in parallel to the first mold surface and the second mold surface; and
a ground conductive via extending from the ground conductive plane through the first mold surface and the second mold surface, and coupled to the first stacked device and the second stacked device,
wherein the ground conductive corridor, the ground conductive plane and the ground conductive via are connected to a ground reference voltage.
8 . The semiconductor package of claim 7 , wherein the ground conductive plane is disposed adjacent the power conductive plane.
9 . The semiconductor package of claim 8 , wherein the ground conductive plane is coupled to the power conductive plane through one or more passive components.
10 . The semiconductor package of claim 9 , wherein each of the one or more passive components is one among a capacitor, a voltage regulator and an inductor.
11 . The semiconductor package of claim 3 , further comprising:
a first redistribution layer disposed on the first die surface and the first mold surface; and
a second redistribution layer disposed on the second die surface and the second mold surface,
wherein the first stacked device is coupled to the silicon die and the first power conductive via through the first redistribution layer, and
the second stacked device is coupled to the silicon die and the second power conductive via through the second redistribution layer.
12 . The semiconductor package of claim 1 , wherein the silicon die is a central processing unit, a graphic processing unit, or a system-on-chip.
13 . The semiconductor package of claim 1 , wherein the first stacked device is a memory device.
14 . The semiconductor package of claim 1 , wherein the second stacked device is a memory device.
15 . A computing device comprising:
a semiconductor package comprising:
a silicon die comprising a first die surface coupled to a package substrate, a second die surface opposite to the first die surface, and at least one die sidewall orthogonal to the first die surface and the second die surface;
a mold layer comprising a first mold surface, a second mold surface opposite to the first mold surface, and at least one mold sidewall orthogonal to the first mold surface and the second mold surface, the at least one mold sidewall being disposed along the at least one die sidewall, and the mold layer further comprising a power conductive corridor extending from the first mold surface and coupled to the package substrate through the first mold surface;
a first stacked device coupled to the first die surface and to the power conductive corridor through the first mold surface; and
a second stacked device coupled to the second die surface and to the power conductive corridor through the second mold surface.
16 . The computing device of claim 15 , wherein the mold layer further comprises:
a power conductive plane extending from the power conductive corridor in parallel to the first mold surface and the second mold surface;
a first power conductive via extending from the power conductive plane through the first mold surface, and coupled to the first stacked device; and
a second power conductive via extending from the power conductive plane through the second mold surface, and coupled to the second stacked device,
wherein the power conductive corridor, the power conductive plane, the first power conductive via and the second power conductive via are connected to a power supply voltage.