IP Library Granted Patent US 11,798,619
Granted Patent B2
US 11,798,619 · App. 17/857,113 · Granted Oct 24, 2023

Precision tuning of a page or word of non-volatile memory cells in an analog neural memory system

Inventors: Hieu Van Tran (San Jose, CA); Thuan Vu (San Jose, CA); Stephen Trinh (San Jose, CA); Stanley Hong (San Jose, CA); Anh Ly (San Jose, CA); Steven Lemke (Boulder Creek, CA); Vipin Tiwari (Dublin, CA); Nhan Do (Saratoga, CA)
Assignee: SILICON STORAGE TECHNOLOGY, INC.
G11C11/54G06N3/065G11C16/0483G11C16/08G11C16/10G11C16/16G11C16/3418G11C2216/04
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Quick Facts
Patent No.
US 11,798,619
App. No.
17/857,113
Granted
Oct 24, 2023
Kind
B2
Abstract

Numerous examples for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. In one example, a method comprises programming a word or page of non-volatile memory cells in an analog neural memory system; and identifying any fast bits in the word or page of non-volatile memory cells.

Claims (14)

1. A method comprising:

programing a word or page of non-volatile memory cells in an analog neural memory system;

identifying any fast bits in the word or page of non-volatile memory cells;

erasing the word or page of non-volatile memory cells;

programming and verifying fast-bits in the word or page of non-volatile memory cells; and

programming and verifying non-fast-bits in the word or page of non-volatile memory cells:

wherein the programming of the fast-bits and the programming of the non-fast-bits utilize different programming sequences.

2. The method of claim 1 , wherein the identifying step comprises monitoring a programming rate of each cell in the word or page.

3. The method of claim 1 , wherein the identifying step comprises monitoring a current change over time during programming of each cell in the word or page.

4. The method of claim 1 , further comprising performing soft programming of the word or page of non-volatile memory cells.

5. The method of claim 1 , wherein the programming and verifying non-fast-bits comprises coarse programing of non-fast-bits.

6. The method of claim 5 , wherein the programming and verifying non-fast-bits comprises fine programming of non-fast-bits.

7. The method of claim 6 , further comprising:

after the fine programming, performing ultra-fine programming of non-fast-bits.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 24, 2025
From: TRAN, HIEU VAN; VU, THUAN; TRINH, STEPHEN; HONG, STANLEY; LY, ANH; LEMKE, STEVEN; TIWARI, VIPIN; DO, NHAN
To: SILICON STORAGE TECHNOLOGY, INC.
Reel/Frame 070602/0737 →