IMAGE SENSOR APPARATUS AND METHOD FOR OBTAINING LOW-NOISE, HIGH-SPEED CAPTURES OF A PHOTOGRAPHIC SCENE
A system, method, and computer program product are provided for obtaining low-noise, high-speed captures of a photographic scene. In use, a first cell of a first pixel is in communication with a first node for storing a first sample. Further, a second cell of a second pixel is in communication with a second node for storing a second sample. Still further, the first cell and the second cell are communicatively coupled.
1 . An image sensor, comprising:
a first analog circuit including a first charge storage element, the first analog circuit in communication with a first node of the first charge storage element for storing a first sample;
a first photodiode in communication with the first analog circuit;
a second photodiode in communication with the first analog circuit;
a second analog circuit including a second charge storage element, the second analog circuit in communication with a second node of the second charge storage element for storing a second sample;
a third photodiode in communication with the second analog circuit;
a fourth photodiode in communication with the second analog circuit; and
a transistor that couples together the first charge storage element with the second charge storage element.
2 . The image sensor of claim 1 , wherein the first sample stored at the first node is based on both of a first light intensity at the first photodiode and a second light intensity at the second photodiode.
3 . The image sensor of claim 1 , wherein the second sample stored at the second node is based on both of a first light intensity at the third photodiode and a second light intensity at the fourth photodiode.
4 . The image sensor of claim 1 , wherein a first sample signal associated with the first sample and a second sample signal associated with the second sample are activated sequentially.
5 . The image sensor of claim 1 , wherein the first sample stored at the first node is based on both of a first light intensity at the first photodiode and a second light intensity at the third photodiode.
6 . The image sensor of claim 1 , wherein the first sample and the second sample are combined together via the first transistor, the combined samples based on a first light intensity at the first photodiode, a second light intensity at the second photodiode, a third light intensity at the third photodiode, and a fourth light intensity at the fourth photodiode.
7 . The image sensor of claim 1 , wherein the transistor includes a drain communicatively coupled to the first node, a source communicatively coupled to the second node, and a gate.
8 . The image sensor of claim 1 , wherein the image sensor is operable such that the first sample is output in a first analog signal.
9 . The image sensor of claim 1 , wherein the image sensor is operable such that a first photodiode current of the first photodiode and a second photodiode current of the second photodiode are combined for storing the first sample at the first node.
10 . The image sensor of claim 9 , wherein the image sensor is operable such that the first sample is output in a first analog signal that is amplified utilizing a first gain, resulting in a first amplified analog signal.
11 . The image sensor of claim 10 , wherein the image sensor is operable such that the first amplified analog signal is converted to at least a portion of a first digital signal associated with a first digital image.
12 . The image sensor of claim 11 , wherein the image sensor is operable such that sliding indicia is displayed, and in response to the sliding indicia being manipulated by a user the first digital signal is blended with a second digital signal associated with a second digital image.
13 . The image sensor of claim 12 , wherein the image sensor is operable such that the second digital signal is generated utilizing, at least in part, a second amplified analog signal, wherein the second amplified analog signal is generated from applying a second gain to a second analog signal, wherein the second analog signal includes an analog value based on the second sample stored at the second node.
14 . The image sensor of claim 13 , wherein the image sensor is operable such that the first sample and the second sample are stored during a single exposure of a photographic scene.
15 . The image sensor of claim 12 , wherein the image sensor is operable such that the first digital signal includes the first digital image having a first resolution, and the second digital signal includes the second digital image having a second resolution different than the first resolution.
16 . The image sensor of claim 15 , wherein the second resolution of the second digital image is greater than the first resolution of the first digital image.
17 . The image sensor of claim 1 , wherein the image sensor is operable such that at least one of the first sample and the second sample is converted to a plurality of digital signals.
18 . The image sensor of claim 17 , wherein the image sensor is operable for transferring the digital signals over a network for being combined remotely.
19 . The image sensor of claim 17 , wherein the image sensor is operable for transferring the digital signals over a network for being combined remotely, resulting in at least a portion of a high dynamic range (HDR) image.
20 . A camera module, comprising:
an image sensor;
a first analog circuit of the image sensor including a first charge storage element, the first analog circuit in communication with a first node of the first charge storage element for storing a first output;
a first photodiode in communication with the first analog circuit;
a second photodiode in communication with the first analog circuit;
a second analog circuit of the image sensor including a second charge storage element, the second analog circuit in communication with a second node of the second charge storage element for storing a second output;
a third photodiode in communication with the second analog circuit;
a fourth photodiode in communication with the second analog circuit; and
a transistor that couples together the first charge storage element with the second charge storage element.