Video decoding apparatus
An image decoding apparatus is implemented that can suppress a decrease in coding efficiency in a case that a high compression rate is achieved. The image decoding apparatus includes a parameter decoder, and the parameter decoder decodes a skip flag indicating whether a skip mode is applied, and in a case that the skip flag does not indicate the skip mode, decodes a merge flag indicating whether a merge mode is applied, and in a case that the merge flag does not indicate the merge mode, decodes an MMVD flag indicating whether an MMVD mode is applied.
1. A video decoding apparatus comprising,
a parameter decoding circuit configured to decode parameters for generating a prediction image in an MMVD mode; and
an MMVD prediction circuit configured to obtain a motion vector by adding a vector difference to a motion vector for merging,
wherein the parameter decoding circuit decodes a first syntax element indicating an index of a merge candidate list, a second syntax element indicating a length of the vector difference, and a third syntax element indicating a direction of the vector difference,
the MMVD prediction circuit
derives the motion vector for merging from the first syntax element,
derives a first vector from the second syntax element and the third syntax element, and
in a case that a distance between a target picture and a L0 picture is equal to a distance between the target picture and a L1 picture, derives the vector difference by scaling the first vector.