Granted Patent B2

US 12,375,588 · App. 17/860,879 · Granted Jul 29, 2025

Inventors: Gregory C. Watson (Palo Alto, CA); Srivathsa Dhruvanarayan (Saratoga, CA); Glen Raymond Gibb (Menlo Park, CA); Constantine Calamvokis (Bath, GB); Aled Justin Edwards (Charfield, GB)

Assignee: Barefoot Networks, Inc.

H04L69/18H04L47/2441H04L49/3009H04L49/3063H04L49/901H04L49/9036H04L49/9042H04L49/9057H04L67/63H04L69/161H04L69/22H04L45/64H04L45/745H04L2212/00

Abstract

Claims (77)

1. An integrated circuit for use in a network, the integrated circuit comprising:

at least one packet processing pipeline for use in processing received frame data to generate egress frame data, the egress frame data to be output via the integrated circuit, the at least one packet processing pipeline comprising:

at least one configurable parser for parsing header field data of the received frame data;

configurable match-action stages for determining, based upon the header field data, at least one corresponding packet processing action to be taken; and

at least one other configurable stage for use in generating the egress frame data; wherein:

when the integrated circuit is in the operation:

the at least one other configurable stage is to generate the egress frame data based upon information to be generated based upon:

(1) egress frame header field-related information that:

 (a) comprises an ordered list that references at least one header field that is to be included in the egress frame data by the at least one other configurable stage; and

 (b) indicates at least one header field location in the egress frame data; and/or

 (c) indicates at least one header field length in the egress frame data; and

(2) checksum-related information that associates at least one checksum that is to be included in the egress frame data by the at least one other configurable stage with another ordered list that references at least one portion of the egress frame data that is to be associated with the at least one checksum.

2. The integrated circuit of claim 1 , wherein:

when the integrated circuit is in operation, the at least one configurable parser, the configurable match-action stages, and the at least one other configurable stage are configurable based upon instructions to be provided to the integrated circuit; and/or

the at least one corresponding packet processing action comprises:

sending the egress frame data to a port associated with the integrated circuit for egress;

modifying at least one header field value;

dropping the received frame data; and/or

buffering the received frame data.

3. The integrated circuit of claim 2 , wherein:

the egress frame header field-related information indicates:

header field locations of packets belonging to multiple protocols; and

which protocol header fields are to be included in the egress frame data.

4. The integrated circuit of claim 3 , wherein:

the header field data corresponds to header field bits of the received frame data that are specifiable in association with parsing-related instructions; and

the parsing-related instructions are usable to indicate (1) next header field data to be parsed based upon preceding header field data and (2) parsing exit.

5. Non-transitory machine-readable storage medium storing instructions that are executable by an integrated circuit, the integrated circuit being for use in a network, the integrated circuit comprising at least one packet processing pipeline for use in processing received frame data to generate egress frame data, the egress frame data to be output via the integrated circuit, the instructions, when executed by the integrated circuit, resulting in the integrated circuit being configurable to perform operations comprising:

parsing, by at least one configurable parser of the at least one packet processing pipeline, header field data of the received frame data;

determining, by configurable match-action stages of the at least one packet processing pipeline, based upon the header field data, at least one corresponding packet processing action to be taken; and

generating, at least in part, by at least one other configurable stage of the at least one packet processing pipeline, the egress frame data;

wherein:

when the integrated circuit is in the operation:

the at least one other configurable stage is to generate the egress frame data based upon information to be generated based upon:

(1) egress frame header field-related information that:

 (a) comprises an ordered list that references at least one header field that is to be included in the egress frame data by the at least one other configurable stage; and

 (b) indicates at least one header field location in the egress frame data; and/or

 (c) indicates at least one header field length in the egress frame data; and

(2) checksum-related information that associates at least one checksum that is to be included in the egress frame data by the at least one other configurable stage with another ordered list that references at least one portion of the egress frame data that is to be associated with the at least one checksum.

6. The non-transitory machine-readable storage medium of claim 5 , wherein:

the at least one corresponding packet processing action comprises:

sending the egress frame data to a port associated with the integrated circuit for egress;

modifying at least one header field value;

dropping the received frame data; and/or

buffering the received frame data.

7. The non-transitory machine-readable storage medium of claim 6 , wherein:

the egress frame header field-related information indicates:

header field locations of packets belonging to multiple protocols; and

which protocol header fields are to be included in the egress frame data.

8. The non-transitory machine-readable storage medium of claim 7 , wherein:

the header field data corresponds to header field bits of the received frame data that are specifiable in association with parsing-related instructions; and

the parsing-related instructions are usable to indicate (1) next header field data to be parsed based upon preceding header field data and (2) parsing exit.

9. A method implemented by an integrated circuit, the integrated circuit being for use in a network, the integrated circuit comprising at least one packet processing pipeline for use in processing received frame data to generate egress frame data, the egress frame data to be output via the integrated circuit, the method comprising:

parsing, by at least one configurable parser of the at least one packet processing pipeline, header field data of the received frame data;

determining, by configurable match-action stages of the at least one packet processing pipeline, based upon the header field data, at least one corresponding packet processing action to be taken; and

generating, at least in part, by at least one other configurable stage of the at least one packet processing pipeline, the egress frame data;

wherein:

when the integrated circuit is in the operation:

the at least one other configurable stage is to generate the egress frame data based upon information to be generated based upon:

(1) egress frame header field-related information that:

 (a) comprises an ordered list that references at least one header field that is to be included in the egress frame data by the at least one other configurable stage; and

 (b) indicates at least one header field location in the egress frame data; and/or

 (c) indicates at least one header field length in the egress frame data; and

(2) checksum-related information that associates at least one checksum that is to be included in the egress frame data by the at least one other configurable stage with another ordered list that references at least one portion of the egress frame data that is to be associated with the at least one checksum.

10. The method of claim 9 , wherein:

when the integrated circuit is in operation, the at least one configurable parser, the configurable match-action stages, and the at least one other configurable stage are configurable based upon instructions to be provided to the integrated circuit; and/or

the at least one corresponding packet processing action comprises:

sending the egress frame data to a port associated with the integrated circuit for egress;

modifying at least one header field value;

dropping the received frame data; and/or

buffering the received frame data.

11. The method of claim 10 , wherein:

the egress frame header field-related information indicates:

header field locations of packets belonging to multiple protocols; and

which protocol header fields are to be included in the egress frame data.

12. The method of claim 11 , wherein:

the header field data corresponds to header field bits of the received frame data that are specifiable in association with parsing-related instructions; and

the parsing-related instructions are usable to indicate (1) next header field data to be parsed based upon preceding header field data and (2) parsing exit.

Continuity (5)

References Cited (400)