IP Library Granted Patent US 12,414,333
Granted Patent B2
US 12,414,333 · App. 17/862,419 · Granted Sep 9, 2025

Semiconductor device

Inventors: Toshiki Kaneko (Tokyo, JP); Akihiro Hanada (Tokyo, JP)
Assignee: Magnolia White Corporation
H10D30/6755H10D30/6729
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Quick Facts
Patent No.
US 12,414,333
App. No.
17/862,419
Granted
Sep 9, 2025
Kind
B2
Abstract

According to one embodiment, a semiconductor device includes a gate electrode, a first insulating layer covering the gate electrode, an oxide semiconductor provided on the first insulating layer immediately above the gate electrode, a source electrode in contact with the oxide semiconductor, and a drain electrode in contact with the oxide semiconductor. Each of the source electrode and the drain electrode includes an oxide conductive layer in contact with the oxide semiconductor, a first metal layer stacked on the oxide conductive layer, a second metal layer formed of a different material from the first metal layer and stacked on the first metal layer, and a third metal layer formed of a same material as the first metal layer and stacked on the second metal layer.

Claims (57)

1. A semiconductor device comprising:

an insulating substrate;

a gate electrode provided on the insulating substrate;

a first insulating layer covering the gate electrode;

an oxide semiconductor provided on the first insulating layer immediately above the gate electrode;

a source electrode in contact with the oxide semiconductor; and

a drain electrode in contact with the oxide semiconductor, wherein

each of the source electrode and the drain electrode comprises:

an oxide conductive layer in contact with the oxide semiconductor;

a first metal layer stacked on the oxide conductive layer;

a second metal layer formed of a different material from the first metal layer, and stacked on the first metal layer; and

a third metal layer formed of a same material as the first metal layer, and stacked on the second metal layer, and

a first side surface of the oxide conductive layer is located on an external side relative to a second side surface of the first metal layer, and

a tilt of the first side surface is less than a tilt of the second side surface.

2. The semiconductor device of claim 1 , wherein

the oxide conductive layer is formed of indium tin oxide or indium zinc oxide.

3. The semiconductor device of claim 1 , wherein

the first metal layer and the third metal layer are formed of a material containing molybdenum (Mo), and

the second metal layer is formed of a material containing aluminum (Al).

4. The semiconductor device of claim 1 , further comprising a passivation film covering the source electrode and the drain electrode, wherein

the oxide conductive layer is in contact with the first insulating layer and the oxide semiconductor, and

the passivation film is in contact with the oxide semiconductor between the source electrode and the drain electrode.

5. A semiconductor device comprising:

an insulating substrate;

a gate electrode provided on the insulating substrate;

a first insulating layer covering the gate electrode;

an oxide semiconductor provided on the first insulating layer immediately above the gate electrode;

a source electrode in contact with the oxide semiconductor;

a drain electrode in contact with the oxide semiconductor;

a second insulating layer covering the oxide semiconductor; and

a passivation film covering the source electrode and the drain electrode, wherein

each of the source electrode and the drain electrode comprises:

an oxide conductive layer in contact with the oxide semiconductor;

a first metal layer stacked on the oxide conductive layer;

a second metal layer formed of a different material from the first metal layer, and stacked on the first metal layer; and

a third metal layer formed of a same material as the first metal layer, and stacked on the second metal layer, and

the oxide conductive layer is in contact with the second insulating layer, and is in contact with the oxide semiconductor in a through-hole of the second insulating layer, and

the passivation film is in contact with the second insulating layer between the source electrode and the drain electrode.

6. A semiconductor device comprising:

an insulating substrate;

a gate electrode provided on the insulating substrate;

a first insulating layer covering the gate electrode;

an oxide semiconductor provided on the first insulating layer immediately above the gate electrode;

a source electrode in contact with the oxide semiconductor;

a drain electrode in contact with the oxide semiconductor;

a passivation film covering the source electrode and the drain electrode; and

a top gate electrode provided on the passivation film and electrically connected to the gate electrode immediately above the gate electrode, wherein

each of the gate electrode, the source electrode, the drain electrode and the top gate electrode comprises:

a first metal layer containing molybdenum (Mo);

a second metal layer containing aluminum (Al) and stacked on the first metal layer; and

a third metal layer containing molybdenum (Mo) and stacked on the second metal layer.

7. The semiconductor device of claim 6 , wherein

each of the source electrode and the drain electrode comprises, as an underlayer of the first metal layer, an oxide conductive layer in contact with the oxide semiconductor.

8. The semiconductor device of claim 6 , further comprising a second insulating layer covering the oxide semiconductor, wherein

the passivation film is in contact with the second insulating layer between the source electrode and the drain electrode.

9. The semiconductor device of claim 6 , wherein

the passivation film is in contact with the oxide semiconductor between the source electrode and the drain electrode.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 27, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 071741/0492 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 12, 2022
From: KANEKO, TOSHIKI; HANADA, AKIHIRO
To: JAPAN DISPLAY INC.
Reel/Frame 060483/0030 →
Priority Claims (1)
JP 2021-115890 · Jul 13, 2021 · national
Continuity (1)
Related Publication 20230017598A1 · Jan 19, 2023
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