Method for PCIe fallback in a CXL system
An information handling system includes a compute express link (CXL) device coupled to a processor by a PCIe/CXL link. The processor initiates a link training on the PCIe/CXL link, determines that the PCIe/CXL link failed to train to a CXL link signaling rate, trains the PCIe/CXL link as a PCIe link in response to determining that the PCIe/CXL link failed to train to the CXL link signaling rate, and operates the CXL device as a PCIe device only in response to training the PCIe/CXL link as a PCIe link.
1. An information handling system, comprising:
a processor; and
a compute express link (CXL) device coupled to the processor by a peripheral component interconnect-express (PCIe)/CXL link;
wherein the processor is configured to initiate a link training on the PCIe/CXL link, to determine that the PCIe/CXL link failed to train to a CXL link signaling rate, to train the PCIe/CXL link as a PCIe link in response to determining that the PCIe/CXL link failed to train to the CXL link signaling rate, to operate the CXL device as a PCIe device only in response to training the PCIe/CXL link as a PCIe link, and to report that the CXL device failed to initialize as a CXL device in response to operating the CXL device as the PCIe device.
2. The information handling system of claim 1 , wherein in training the PCIe/CXL link as the PCIe link, the processor is further configured to set a flag indicating that the PCIe/CXL link failed to train at the CXL link signaling rate.
3. The information handling system of claim 2 , wherein in training the PCIe/CXL link as the PCIe link, the processor is further configured to reset the CXL device.
4. The information handling system of claim 3 , wherein in response to resetting the CXL device, the processor is further configured to read the flag.
5. The information handling system of claim 4 , wherein training the PCIe/CXL link as the PCIe link is in response to reading the flag.
6. The information handling system of claim 2 , wherein the flag is in a non-volatile memory associated with the processor.
7. The information handling system of claim 2 , wherein the flag is in a non-volatile memory of the CXL device.
8. The information handling system of claim 1 , wherein in operating the CXL device as the PCIe device, the processor is further configured to repurpose a CXL queue associated with the CXL device to the PCIe device.
9. The information handling system of claim 1 , wherein in operating the CXL device as the PCIe device, the processor is further configured to utilize a PCIe device driver associated with the CXL device in accessing the PCIe device.
10. A method, comprising:
coupling a processor to a compute express link (CXL) device by a peripheral component interconnect-express (PCIe)/CXL link;
initiating, by the processor, a link training on the PCIe/CXL link;
determining that the PCIe/CXL link failed to train to a CXL link signaling rate;
training the PCIe/CXL link as a PCIe link in response to determining that the PCIe/CXL link failed to train to the CXL link signaling rate;
operating the CXL device as a PCIe device only in response to training the PCIe/CXL link as a PCIe link; and
in operating the CXL device as the PCIe device, repurposing a CXL queue associated with the CXL device to the PCIe device.
11. The method of claim 10 , wherein in training the PCIe/CXL link as the PCIe link, the method further comprises setting set a flag indicating that the PCIe/CXL link failed to train at the CXL link signaling rate.
12. The method of claim 11 , wherein in training the PCIe/CXL link as the PCIe link, the processor is further configured to reset the CXL device.
13. The information handling system of claim 12 , wherein in response to resetting the CXL device, the method further comprises reading the flag.
14. The method of claim 13 , wherein training the PCIe/CXL link as the PCIe link is in response to reading the flag.
15. The method of claim 11 , wherein the flag is in one of a non-volatile memory associated with the processor, and a non-volatile memory of the CXL device.
16. The method of claim 10 , wherein in operating the CXL device as the PCIe device, the method further comprises utilizing a PCIe device driver associated with the CXL device in accessing the PCIe device.
17. The method of claim 10 , further comprising reporting that the CXL device failed to initialize as a CXL device in response to operating the CXL device as the PCIe device.
18. An information handling system, comprising:
a processor; and
a compute express link (CXL) device coupled to the processor by a peripheral component interconnect-express (PCIe)/CXL link;
wherein the processor is configured to initiate a link training on the PCIe/CXL link, to determine that the PCIe/CXL link failed to train to a CXL link signaling rate, to set a flag indicating that the PCIe/CXL link failed to train at the CXL link signaling rate, to train the PCIe/CXL link as a PCIe link in response to determining that the PCIe/CXL link failed to train to the CXL link signaling rate, to operate the CXL device as a PCIe device only in response to training the PCIe/CXL link as a PCIe link, and to report that the CXL device failed to initialize as a CXL device in response to operating the CXL device as the PCIe device.