IP Library Granted Patent US 12,015,481
Granted Patent B1
US 12,015,481 · App. 17/866,825 · Granted Jun 18, 2024

Q margin

Inventors: Yue Pan (Boston, MA); Jonas Geyer (Somerville, MA)
Assignee: Acacia Technology, Inc.
H04L1/0057H03M13/03H03M13/43H04L1/0041H04L1/0045H04L1/0618
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Quick Facts
Patent No.
US 12,015,481
App. No.
17/866,825
Granted
Jun 18, 2024
Kind
B1
Abstract

A method, system, and ASIC chip for comparing a bit error rate (BER) to a forward error correction (FEC) threshold to determine a Q margin for a codeblock; wherein the BER corresponds to the number of errors in a given amount of data; where a codeblock of a FEC corresponds to the given amount of data; wherein the FEC threshold corresponds to the maximum amount of errors per codeblock that the FEC is able to remove per given amount of data; wherein the Q margin corresponds to a difference between the BER and the FEC threshold.

Claims (39)

1. A method comprising:

receiving at least one of a plurality of forward error correction (FEC) codeblocks transmitted across an optical link, wherein each of the plurality of FEC codeblocks corresponds to a portion of data bits provided to a FEC in a given time interval;

measuring a bit error rate (BER) for each of the plurality of FEC codeblocks, wherein the BER for each of the plurality of FEC codeblocks corresponds to an amount of errors in the corresponding portion of data bits; and determining a maximum BER of the measured BERs;

determining a Q margin for an FEC codeblock of the plurality of FEC codeblocks corresponding to the maximum BER by comparing the maximum BER with a FEC threshold, wherein the FEC threshold corresponds to a maximum amount of errors per FEC codeblock of the plurality of FEC codeblocks that the FEC is able to correct; and

reporting each of the plurality of FEC codeblocks and the measured BER for each of the plurality of FEC codeblocks based on the Q margin exceeding the FEC threshold, and wherein each of the plurality of FEC codeblocks is discarded based on the Q margin exceeding the FEC threshold.

2. The method of claim 1 wherein the measured BER for each of the plurality of FEC codeblocks is a function of a signal-to-noise ratio.

3. The method of claim 1 wherein the FEC further comprises an interleaver to redistribute data of an original time interval to at least one different time interval; and a deinterleaver to redistribute data of the at least one different time interval to the original time interval.

4. The method of claim 1 wherein the data bits are data converted from an optical signal.

5. The method of claim 4 wherein the errors comprise errors introduced during transmission of the optical signal.

6. The method of claim 1 wherein the FEC comprises a first transceiver and a second transceiver, wherein the first transceiver comprises an encoder to encode a signal, and wherein the second transceiver comprises a decoder to decode the encoded signal.

7. The method of claim 6 wherein the encoded signal is transmitted from the encoder of the first transceiver to the decoder of the second transceiver.

8. An application-specific integrated circuit (ASIC) chip comprising:

Forward Error Correction (FEC); and

logic enabling:

receiving at least one of a plurality of FEC codeblocks transmitted across an optical link; wherein each of the plurality of FEC codeblocks correspond to a portion of data bits provided to the FEC in a given time interval;

measuring a bit error rate (BER) for each of the plurality of FEC codeblocks, wherein the BER for each of the plurality of FEC codeblocks corresponds to an amount of errors in the corresponding portion of data bits; and determining a maximum BER of the measured BERs;

determining a Q margin for an FEC codeblock of the plurality of FEC codeblocks corresponding to the maximum BER by comparing the maximum BER with a FEC threshold, wherein the FEC threshold corresponds to a maximum amount of errors per FEC codeblock of the plurality of FEC codeblocks that the FEC is able to correct; and

reporting each of the plurality of FEC codeblocks and the measured BER for each of the plurality of FEC codeblocks based on the Q margin exceeding the FEC threshold, and wherein each of the plurality of FEC codeblocks are discarded based on the Q margin exceeding the FEC threshold.

9. The ASIC chip of claim 8 wherein the measured BER for each of the plurality of FEC codeblocks is a function of a signal-to-noise ratio.

10. The ASIC chip of claim 8 wherein the FEC further comprises an interleaver to redistribute data of an original time interval to at least one different time interval; and a deinterleaver to redistribute data of the at least one different time interval to the original time interval.

11. The ASIC chip of claim 8 , wherein the data bits are data converted from an optical signal.

12. The ASIC chip of claim 11 , wherein the errors comprise errors introduced during transmission of the optical signal.

13. The ASIC chip of claim 8 , wherein the FEC comprises a first transceiver and a second transceiver, wherein the first transceiver comprises an encoder, wherein the second transceiver comprises a decoder, and wherein the logic further enables:

encoding, by the encoder of the first transceiver, a signal; and

decoding, by the decoder of the second transceiver, the encoded signal.

14. The ASIC chip of claim 13 wherein the encoded signal is transmitted from the encoder of the first transceiver to the decoder of the second transceiver.

15. A system comprising:

a first transceiver comprising a first application-specific integrated circuit (ASIC) chip; wherein the first transceiver further comprises a first forward error correction (FEC) element of a FEC;

a second transceiver comprising a second ASIC chip; wherein the second transceiver further comprises a second FEC element of the FEC; and

logic enabling:

receiving at least one of a plurality of FEC codeblocks transmitted across an optical link; wherein each of the plurality of FEC codeblocks correspond to a portion of data bits provided to the FEC in a given time interval;

measuring a bit error rate (BER) for each of the plurality of FEC codeblocks, wherein the BER for each of the plurality of FEC codeblocks corresponds to an amount of errors in the corresponding portion of data bits; and determining a maximum BER of the measured BERs;

determining a Q margin for an FEC codeblock of the plurality of FEC codeblocks corresponding to the maximum BER by comparing the maximum BER with a FEC threshold, wherein the FEC threshold corresponds to a maximum amount of errors per FEC codeblock of the plurality of FEC codeblocks that the FEC is able to correct; and

reporting each of the plurality of FEC codeblocks and the measured BER for each of the plurality of FEC codeblocks based on the Q margin exceeding the FEC threshold, and wherein each of the plurality of FEC codeblocks are discarded based on the Q margin exceeding the FEC threshold.

16. The system of claim 15 , wherein the measured BER for each of the plurality of FEC codeblocks is a function of a signal-to-noise ratio.

17. The system of claim 15 , wherein the FEC further comprises an interleaver to redistribute data of an original time interval to at least one different time interval; and a deinterleaver to redistribute data of the at least one different time interval to the original time interval.

18. The system of claim 15 , wherein the data bits are data converted from an optical signal.

19. The system of claim 18 , wherein the optical signal is transmitted from the first transceiver to the second transceiver.

20. The system of claim 15 , wherein the first FEC element of the FEC is an encoder, and wherein the second FEC element of the FEC is a decoder.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 19, 2024
From: ACACIA COMMUNICATIONS, INC.
To: ACACIA TECHNOLOGY, INC.
Reel/Frame 066832/0659 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2023
From: PAN, YUE; GEYER, JONAS
To: ACACIA COMMUNICATIONS, INC.
Reel/Frame 063641/0622 →
Continuity (1)
Continuation 16722300 · Dec 20, 2019