Memory devices and methods having multiple acknowledgements in response to a same instruction

1. A method, comprising:

at an interface of a memory device,

receiving an operational code (op code) on a serial bus as a sequence of no less than 16-bit values in synchronism with a serial clock signal; and

receiving an error code with each op code at the interface;

by operation of controller circuits of the memory device,

generating a plurality of acknowledgement values in response to each received op code, the acknowledgement values each being a multi-bit value, and

determining if the error code corresponds to the op code with which the error code was received to verify the op code; and

by operation of memory circuits of the memory device, executing or not executing a memory access operation to memory cell arrays of the memory device as indicated by the op code; wherein

in response to the memory access operation being executed by the memory circuits and the error code verifying the op code, the controller circuit generating a first acknowledgement value and a second acknowledgement value for output at the interface, and

in response to the memory access operation not being executed by the memory circuits and the error code verifying the op code, the controller circuit generating the first acknowledgement value and a third acknowledgement value for output at the interface.

2. The method of claim 1 , wherein:

in response to the memory access operation being executed by the memory circuits, the first acknowledgement value is presented at the interface before the second acknowledgement value; and

in response to the memory access operation not being executed by the memory circuits, the first acknowledgement value is presented at the interface before the third acknowledgement value.

3. The method of claim 1 , wherein each of the acknowledgement values has the same bit size as the op code.

4. The method of claim 1 , further including storing the acknowledgement values in status registers of the interface.

5. The method of claim 1 , further including:

in response to the memory access operation being executed by the memory circuits, outputting the first acknowledgement value followed by the second acknowledgement value on the serial bus; and

in response to the memory access operation not being executed by the memory circuits, outputting the first acknowledgement value followed by the third acknowledgement value on the serial bus.

6. The method of claim 5 , wherein the first, second and third acknowledgement values are different sequences of no less than 16-bit values output in synchronism with the serial clock signal.

7. A memory device, comprising:

a serial interface (IF) that includes a serial clock input and at least one serial data input, the serial IF configured to

receive an operational code (op code) of no less than 16-bits on the serial data input in synchronism with a serial clock signal received at the serial clock input,

receive an error code with the op code, and

provide a plurality of acknowledgement values in response to the received op code;

controller circuits that include error check circuits and are configured to generate the plurality of acknowledgement values, including

first and second acknowledgement values in response to an operation indicated by the op code being completed and the error check circuits verifying the op code with the error code received with the op code, and

first and third acknowledgement values in response to an operation indicated by the op code not being completed and the error check circuits verifying the op code with the error code received with the op code; and

memory circuits that include at least one array of nonvolatile memory cells and at least one array of volatile memory cells, the memory circuits configured to

execute the operation indicated by the op code to access the nonvolatile memory cells, and

indicate to the controller circuits if the operation was completed or if the operation was not completed; wherein

the first, second and third acknowledgement values are different multi-bit values.

8. The memory device of claim 7 , wherein the serial IF further includes a serial output and is configured to output the plurality of acknowledgements on the serial output.

9. The memory device of claim 7 , wherein the serial IF further includes a plurality of status registers configured to store the plurality of acknowledgements.

10. The memory device of claim 7 , wherein:

the serial IF is further configured to

provide the first acknowledgment value before the second acknowledgment value, and

provide the first acknowledgment value before the third acknowledgment value.

11. The memory device of claim 7 , wherein each of the acknowledgement values has the same bit size as the op code.

12. The memory device of claim 7 , wherein the serial IF, controller circuits and memory circuits are all formed in the same integrated circuit substrate.

13. A system, comprising:

a memory device having

a serial interface (IF) coupled to a serial bus and configured to

receive an operational code (op code) of no less than 16-bits from the serial bus in synchronism with a serial clock signal,

receive an error code with the op code, and

provide a plurality of acknowledgement values in response to the received op code;

controller circuits that include error check circuits and are configured to generate the plurality of acknowledgement values, including

first and second acknowledgement values in response to an operation indicated by the op code being completed and the error check circuits verify the op code with the error code received with the op code, and

first and third acknowledgement values in response to an operation indicated by the op code not being completed and the error check circuits verify the op code with the error code received with the op code, and

memory circuits that include at least one array of memory cells and configured to execute the operation indicated by the op code to access the memory cells and indicate to the controller circuits if the operation was completed or if the operation was not completed; and

a host device coupled to the serial bus and configured to transmit the op code to the memory device.

14. The system of claim 13 , wherein:

the serial interface includes status registers configured to store the acknowledgement values; and

the host device is further configured to read the acknowledgement values from the memory device status registers over the serial bus.

15. The system of claim 14 , wherein the host device is configured to read the first acknowledgement value prior to the second and third acknowledgement values.

16. The system of claim 13 , wherein each of the acknowledgement values has the same bit size as the op code.

17. The system of claim 13 , wherein:

the serial IF is further configured to

provide the first acknowledgment value before the second acknowledgment value, and

provide the first acknowledgment value before the third acknowledgment value.