Deep vision processor

1. A processor comprising:

a banked register file configured to store image pixel data;

an interconnect unit configured to access:

multiple subsets of the image pixel data from the banked register file; and

corresponding stencil data for the multiple subsets of image pixel data; and

a set of arithmetic logic units configured to concurrently execute a set of one-dimensional stencil operations on subsets of the image pixel data and corresponding stencil data, the set of one-dimensional stencil operations representing a multi-dimensional stencil operation.

2. The processor of claim 1 , wherein the set of arithmetic logic units is configured to concurrently execute a set of smaller convolution operations on each subset of the image pixel data and corresponding stencil data, the set of smaller convolution operations:

characterized by a set of smaller kernel sizes; and

representing a larger convolution operation on the image pixel data characterized by a larger kernel size.

3. The processor of claim 2 , wherein the set of arithmetic logic units is configured to concurrently execute the set of smaller convolution operations on each subset of the image pixel data and the corresponding stencil data, the set of smaller convolution operations:

representing the larger convolution operation on the image pixel data characterized by the larger kernel size; and

characterized by the set of smaller kernel sizes selected from a group of kernel sizes comprising:

a three-by-three kernel size;

a four-by-four kernel size;

a one-by-three kernel size;

a three-by-one kernel size;

a one-by-four kernel size; and

a four-by-one kernel size.

4. The processor of claim 2 , wherein the set of arithmetic logic units is configured to concurrently execute the set of smaller convolution operations on each subset of the image pixel data and the corresponding stencil data, the set of smaller convolution operations representing the larger convolution operation on the image pixel data characterized by the larger kernel size selected from a group of kernel sizes comprising:

a five-by-five kernel size;

a seven-by-seven kernel size;

an eight-by-eight kernel size;

a one-by-five kernel size;

a one-by-seven kernel size;

a one-by-eight kernel size;

a five-by one kernel size;

a seven-by-one kernel size; and

an eight-by-one kernel size.

5. The processor of claim 1 , wherein the banked register file represents a two-dimensional register abstraction.

6. The processor of claim 1 , wherein the multi-dimensional stencil operation comprises a two-dimensional stencil operation.

7. A processor comprising:

a shift register unit:

configured to store image pixel data; and

representing a multi-dimensional register abstraction;

a mapping unit in communication with the shift register unit:

configured to concurrently access multiple subsets of the image pixel data from the shift register unit based on a multi-dimensional stencil pattern within the multi-dimensional register abstraction;

configured to concurrently access corresponding stencil data for each subset of the image pixel data in the multiple subsets of the image pixel data; and

comprising a set of arithmetic logic units configured to concurrently execute a set of operations on each subset of the image pixel data and the corresponding stencil data, the set of operations representing a stencil operation characterized by the multi-dimensional stencil pattern.

8. The processor of claim 7 , wherein the mapping unit is configured to concurrently access the multiple subsets of the image pixel data, each subset of the image pixel data defining a smaller stencil pattern in a set of smaller stencil patterns, the set of smaller stencil patterns combining to define the multi-dimensional stencil pattern.

9. The processor of claim 7 :

wherein the set of arithmetic logic units is further configured to generate a set of outputs resulting from the set of operations; and

further comprising a reduction unit, configured to combine the set of outputs to generate a reduced output of the stencil operation.

10. The processor of claim 9 :

wherein the set of arithmetic logic units is configured to concurrently execute a set of multiplication operations to generate the set of outputs; and

wherein the reduction unit is configured to execute a summation operation on the set of outputs to generate the reduced output.

11. The processor of claim 9 , wherein the set of arithmetic logic units are configured to concurrently execute a set of subtraction operations to generate the set of outputs.

12. The processor of claim 9 :

wherein the set of arithmetic logic units are configured to concurrently execute a set of absolute difference operations to generate the set of outputs; and

wherein the reduction unit is configured to execute a summation operation on the set of outputs to generate the reduced output.

13. The processor of claim 9 , wherein the set of arithmetic logic units are configured to concurrently execute a set of averaging operations to generate the set of outputs.

14. The processor of claim 9 , further comprising a set of accumulator registers configured to accumulate a set of reduced outputs comprising the reduced output to execute the stencil operation.

15. The processor of claim 9 , further comprising an output register implemented as a shift register and configured to access the set of outputs from the mapping unit.

16. The processor of claim 7 , further comprising a single-input-multiple-data unit configured to execute general purpose computations.

17. A register unit of a processor core:

comprising a set of register banks;

configured to store image pixel data within the set of register banks;

representing a multi-dimensional register abstraction; and

configured to provide access to multiple subsets of the image pixel data in the set of register banks, the multiple subsets of the image pixel data defining a multi-dimensional stencil pattern within the multi-dimensional register abstraction.