Mitigating a voltage condition of a memory cell in a memory sub-system
A determination that a first programming operation has been performed on a particular memory cell can be made. A determination can be made, based on one or more threshold criteria, whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate. In response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, an operation can be performed on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.
1. A system comprising:
a memory; and
a processing device communicably coupled to the memory, the processing device to:
determine that a first programming operation has been performed on a particular memory cell;
determine, based on one or more threshold criteria, whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate; and
in response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, perform an operation on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.
2. The system of claim 1 , wherein to determine, based on one or more threshold criteria, whether the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, the processing device is further to:
identify an amount of time that has elapsed since the first programming operation has been performed on the particular memory cell; and
determine whether the amount of time that has elapsed satisfies a threshold time condition.
3. The system of claim 2 , wherein the amount of time that has elapsed satisfies the threshold time condition when the amount of time is equal to or exceeds a threshold amount of time.
4. The system of claim 2 , wherein the processing device is further to:
in response to determining that the amount of time that has elapsed does not satisfy the threshold time condition, determine to not perform the operation on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.
5. The system of claim 2 , wherein the first programming operation stores data at the particular memory cell, and wherein the identified amount of time that has elapsed corresponds to an elapsed time since the data was stored at the particular memory cell without a subsequent programming operation being performed at the particular memory cell.
6. The system of claim 1 , wherein the operation on the particular memory cell to transition the particular memory cell comprises an operation to change or maintain a voltage condition of the particular memory cell.
7. The system of claim 1 , wherein the state associated with the increased error rate is a stable threshold voltage state of the particular memory cell, and wherein the another state associated with the decreased error rate is a transient threshold voltage state of the particular memory cell.
8. The system of claim 1 , wherein the processing device is further to:
determine that a second programming operation has not been performed on the particular memory cell, wherein performing the operation on the particular memory cell to transition the particular memory cell is further in response to determining that the second programming operation has not been performed on the particular memory cell.
9. The system of claim 8 , wherein the first programming operation corresponds to a first pass of a two-pass programming operation, and the second programming operation corresponds to a second pass of the two-pass programming operation.
10. The system of claim 1 , wherein the increased error rate corresponds to a higher number of errors than the decreased error rate.
11. The system of claim 1 , wherein the one or more threshold criteria comprise a number of operations that have been performed on one or more memory cells that are proximate to the particular memory cell.
12. The system of claim 11 , wherein the state associated with the decreased error rate corresponds to a transient threshold voltage state of the particular memory cell and the another state associated with the increased error rate corresponds to a stable threshold voltage state of the particular memory cell, and wherein data stored at the particular memory cell is retrieved with fewer errors when the particular memory cell is at the transient threshold voltage state than when the particular memory cell is at the stable threshold voltage state.
13. The system of claim 11 , wherein determining, based on the one or more threshold criteria, whether the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with an increased error rate comprises:
determining whether the number of operations that have been performed on the one or more memory cells is equal to or exceeds a threshold number of operations, wherein the particular memory cell is determined to have transitioned to the another state associated with the increased error rate when the number of operations is equal to or exceeds the threshold number of operations.
14. The system of claim 11 , wherein the operation on the particular memory cell is a read operation or an application of a voltage.
15. The system of claim 11 , wherein the one or more memory cells that are proximate to the particular memory cell are located on a same word line as the particular memory cell, wherein the one or more memory cells that are proximate to the particular memory cell correspond to a data block that is at a same plane of another data block that includes the particular memory cell.
16. The system of claim 11 , wherein the operations that have been performed on the one or more memory cells are write operations or erase operations.
17. A method comprising:
determining that a first programming operation has been performed on a particular memory cell;
determining, based on one or more threshold criteria, whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate; and
in response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, performing, by a processing device, an operation on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.
18. The method of claim 17 , wherein determining, based on one or more threshold criteria, whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate comprises:
identifying an amount of time that has elapsed since the first programming operation has been performed on the particular memory cell; and
determining whether the amount of time that has elapsed satisfies a threshold time condition.
19. A non-transitory machine-readable storage medium storing instructions that cause a processing device to perform operations comprising:
determining that a first programming operation has been performed on a particular memory cell;
determining, based on one or more threshold criteria, whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate; and
in response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, performing, by a processing device, an operation on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.
20. The non-transitory machine-readable storage medium of claim 19 , wherein determining, based on one or more threshold criteria, whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate comprises:
identifying an amount of time that has elapsed since the first programming operation has been performed on the particular memory cell; and
determining whether the amount of time that has elapsed satisfies a threshold time condition.