Granted Patent B2

US 12,316,725 · App. 17/870,716 · Granted May 27, 2025

Inventors: Su-Lin Low (San Diego, CA); Tianan Tim Ma (San Diego, CA); Hausting Hong (San Diego, CA); Hong Kui Yang (San Diego, CA); Jian Gu (San Diego, CA); Anna Gontar (San Diego, CA)

Assignee: GREATER SHINE LIMITED

H04L69/324H04L1/0061

Abstract

Claims (51)

1. An apparatus, comprising:

at least one processor; and

at least one memory including computer program code,

wherein the at least one memory and the computer program code are configured to, with the at least one processor, cause the apparatus at least to:

decode a physical layer code block or a physical layer code block group;

decode a medium access control (MAC) sub-packet corresponding to the decoded physical layer code block or the physical code block group without waiting for any subsequent physical layer code blocks to be decoded; and

pass the decoded MAC sub-packet up a protocol stack;

wherein a size of the physical layer code block or the physical layer code block group is aligned with a size of the MAC sub-packet, at an upper layer of the protocol stack;

alignment of the size of the physical layer code block or the physical layer code block group with the size of the MAC sub-packet comprises a one-to-one relationship between the physical layer code block or the physical layer code block group and the MAC sub-packet.

2. The apparatus of claim 1 , wherein the MAC sub-packet comprises a downlink MAC sub-packet.

3. The apparatus of claim 1 , wherein the MAC sub-packet comprises a MAC sub-protocol data unit (MACSubPDU) packet.

4. The apparatus of claim 1 , wherein the at least one memory and the computer program code are configured to, with the at least one processor, cause the apparatus at least to:

receive the decoded MAC sub-packet at a MAC layer; and

pass a payload of the MAC sub-packet up the protocol stack without waiting for a subsequent MAC sub-packet to be decoded.

5. The apparatus of claim 1 , wherein the at least one memory and the computer program code are configured to, with the at least one processor, cause the apparatus at least to:

pass the decoded MAC sub-packet up the protocol stack by, for each of a plurality of protocol layers of the stack, reading and removing a layer-specific header for a given layer of the protocol stack; and

passing a payload portion of the MAC sub-packet to an adjacent layer of the protocol stack.

6. A method for code block processing, comprising:

decoding a physical layer code block or a physical layer code block group;

decoding a medium access control (MAC) sub-packet corresponding to the decoded physical layer code block or the physical code block group without waiting for any subsequent physical layer code blocks to be decoded; and

passing the decoded MAC sub-packet up a protocol stack;

wherein a size of the physical layer code block or the physical layer code block group is aligned with a size of the MAC sub-packet, at an upper layer of the protocol stack;

alignment of the size of the physical layer code block or the physical layer code block group with the size of the MAC sub-packet comprises a one-to-one relationship between the physical layer code block or the physical layer code block group and the MAC sub-packet.

7. The method of claim 6 , wherein the MAC sub-packet comprises a downlink MAC sub-packet.

8. The method of claim 6 , wherein the MAC sub-packet comprises a MAC sub-protocol data unit (MACSubPDU) packet.

9. The method of claim 6 , further comprising:

receiving the decoded MAC sub-packet at a media access control layer; and

passing a payload of the MAC sub-packet up the protocol stack without waiting for a subsequent MAC sub-packet to be decoded.

10. The method of claim 6 , wherein the passing the decoded MAC sub-packet up the protocol stack comprises, for each of a plurality of protocol layers of the stack, reading and removing a layer-specific header for a given layer of the protocol stack and passing a payload portion of the MAC sub-packet to an adjacent layer of the protocol stack.

11. An apparatus, comprising:

at least one processor; and

at least one memory including computer program code,

wherein the at least one memory and the computer program code are configured to, with the at least one processor, cause the apparatus at least to:

align a sub-packet with a physical layer boundary, wherein a packet comprises the sub-packet and a plurality of other sub-packets; and

forward for transmission the sub-packet bounded by the physical layer boundary.

12. The apparatus of claim 11 , wherein the sub-packet comprises a downlink sub-packet.

13. The apparatus of claim 11 , wherein the sub-packet comprises a medium access control (MAC) sub-protocol data unit (MACSubPDU) packet.

14. The apparatus of claim 11 , wherein the physical layer boundary is at least one of a code block boundary or a code block group boundary.

15. The apparatus of claim 11 , wherein the at least one memory and the computer program code are configured to, with the at least one processor, cause the apparatus at least to:

receive a plurality of layer 3 packets for communication;

generate packet data units based on the received layer 3 packets; and

queue the packet data units in layer 2 logical channels,

wherein the aligning the sub-packet comprises aligning one of the packet data units in one of the layer 2 logical channels.

16. The apparatus of claim 15 , wherein the packet data units comprise packet data convergence protocol (PDCP) packet data units.

17. The apparatus of claim 11 , wherein the at least one memory and the computer program code are configured to, with the at least one processor, cause the apparatus at least to align the sub-packet by a process comprising segmenting a transport block into code blocks taking to account a bit amount of cyclic redundancy check bits.

18. The apparatus of claim 17 , wherein the segmenting comprises:

identifying a code block size by a physical layer;

providing the code block size to a MAC layer, and

composing a plurality of MACSubPDU packets in the MAC layer corresponding to the code block size.

19. The apparatus of claim 11 , wherein a size of a physical layer code block or a physical layer code block group is aligned with a size of the sub-packet, at an upper layer of a protocol stack;

alignment of the size of the physical layer code block or the physical layer code block group with the size of the sub-packet comprises a one-to-one relationship between the physical layer code block or the physical layer code block group and the sub-packet.

Assignments (4)

Continuity (3)

References Cited (22)