Semiconductor device structure

1. A method, comprising:

receiving a substrate comprising a p-type well and an n-type well adjoining the p-type well at an interface;

forming a semiconductor stack over the substrate, the semiconductor stack comprising a plurality of channel layers interleaved by a plurality of sacrificial layers;

patterning the semiconductor stack and a portion of the substrate to form a first fin and a second fin over the p-type well and a third fin and a fourth fin over the n-type well, the first fin and second fin being spaced apart by a first trench, the second fin and third fin being spaced part by a second trench, the third fin and fourth fin being spaced apart by a third trench;

depositing a liner over the first trench, the second trench and the third trench;

extending the second trench into the interface to form a deep well;

depositing a dielectric material in the deep well, the first trench and the third trench;

etching back the dielectric material to form a first isolation feature in the first trench, a deep isolation feature and a junction isolation feature in the second trench, and a second isolation feature in the third trench;

forming a first dielectric fin in the first trench and over the first isolation feature and a second dielectric fin in the third trench and over the second isolation feature; and

forming a junction dielectric fin in the second trench over the junction isolation feature.

2. The method of claim 1 ,

wherein the second trench comprises a first spacing,

wherein each of the first trench and the third trench comprises a second spacing smaller than the first spacing.

3. The method of claim 2 ,

wherein the first spacing is between about 20 nm and about 30 nm,

wherein the second spacing is between about 10 nm and about 20 nm.

4. The method of claim 1 , wherein the forming of the first dielectric fin and the second dielectric fin comprises:

conformally depositing a first dielectric layer over the first trench, the second trench and the third trench;

depositing a second dielectric layer over the first dielectric layer in the first trench, the second trench and the third trench; and

etching back the first dielectric layer and the second dielectric layer to expose top surfaces of the first fin, the second fin, the third fin, and the fourth fin.

5. The method of claim 4 , wherein the etching back also removes the first dielectric layer and the second dielectric layer in the second trench to expose the junction isolation feature.

6. The method of claim 4 , wherein the forming of the junction dielectric fin comprises:

selectively depositing a cladding layer over sidewalls of the second fin and the third fin exposed in the second trench;

conformally depositing a third dielectric layer over the second trench; and

depositing a fourth dielectric layer over the third dielectric layer.

7. The method of claim 6 , further comprising:

selectively etching back the first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer to form a first recess directly over the first dielectric fin, a second recess directly over the junction isolation feature, and a third recess directly over the second dielectric fin.

8. The method of claim 7 , further comprising:

forming a first helmet layer in the first recess, a second helmet layer in the second recess, and a third helmet layer in the third recess.

9. The method of claim 1 , further comprising:

forming a dummy gate stack over channel regions of the first fin, the second fin and the third fin;

forming a gate spacer layer over sidewalls of the dummy gate stack;

etching the first fin, the second fin and the third fin using the dummy gate stack and the gate spacer layer as an etch mask;

removing the dummy gate stack;

selectively removing the plurality of sacrificial layers in the channel regions to release the plurality of channel layers as channel members; and

forming a gate structure to wrap around each of the channel members.

10. A method, comprising:

receiving a workpiece comprising:

a substrate comprising a p-type well and an n-type well adjoining the p-type well at an interface,

a first fin-shaped structure and a second fin-shaped structure over the p-type well, wherein the first fin-shaped structure is spaced apart from the second fin-shaped structure by a first spacing, and

a third fin-shaped structure over the n-type well, wherein the third fin-shaped structure is spaced apart from the second fin-shaped structure by a second spacing greater than the first spacing;

depositing a liner over sidewalls of the first fin-shaped structure, the second fin-shaped structure, and the third fin-shaped structure;

after the depositing of the liner, forming a deep pocket between the second fin-shaped structure and the third fin-shaped structure;

depositing a dielectric material in the deep pocket, in the first spacing and the second spacing;

etching back the dielectric material to form a first isolation feature between the first fin-shaped structure and the second fin-shaped structure, a deep isolation feature and a junction isolation feature between the second fin-shaped structure and the third fin-shaped structure;

forming a first dielectric fin over the first isolation feature; and

forming a junction dielectric fin over the junction isolation feature.

11. The method of claim 10 , wherein the liner comprises silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride.

12. The method of claim 10 , wherein the deep pocket undercuts the liner.

13. The method of claim 10 ,

wherein the first spacing is between about 10 nm and about 20 nm,

wherein the second spacing is between about 20 nm and about 30 nm.

14. The method of claim 10 , wherein the forming of the junction dielectric fin comprises:

selectively depositing a cladding layer over sidewalls of the second fin-shaped structure and the third fin-shaped structure exposed in the second spacing;

conformally depositing a first dielectric layer between the second fin-shaped structure and the third fin-shaped structure; and

depositing a second dielectric layer over the first dielectric layer.

15. The method of claim 14 , wherein the cladding layer comprises silicon germanium.

16. A method, comprising:

receiving a workpiece including a first fin-shaped structure over a p-type well region of a substrate and a second fin-shaped structure over an n-type well region of the substrate, the first fin-shaped structure and the second fin-shaped structure being spaced apart by a junction trench;

extending the junction trench further into the substrate to form a deep pocket;

forming a deep isolation feature in the deep pocket and an isolation feature in the junction trench; and

forming a dielectric fin on the isolation feature such that the dielectric fin is disposed between the first fin-shaped structure and the second fin-shaped structure.

17. The method of claim 16 , further comprising:

before the extending of the junction trench, forming a liner along sidewalls of the junction trench.

18. The method of claim 17 , wherein the forming of the deep isolation feature and the isolation feature comprises:

depositing a dielectric material into the deep pocket and the junction trench; and

etching back the liner and the dielectric material to expose sidewalls of the first fin-shaped structure and the second fin-shaped structure.

19. The method of claim 18 , further comprising:

before the forming of the dielectric fin, depositing a semiconductor cladding layer over the sidewalls of the first fin-shaped structure and the second fin-shaped structure.

20. The method of claim 19 , wherein, after the forming of the dielectric fin, the dielectric fin is spaced apart from the first fin-shaped structure and the second fin-shaped structure by the semiconductor cladding layer.