Memory device and method for forming the same
A memory device includes a substrate, first semiconductor fin, second semiconductor fin, first gate structure, second gate structure, first gate spacer, and a second gate spacer. The first gate structure crosses the first semiconductor fin. The second gate structure crosses the second semiconductor fin, the first gate structure extending continuously from the second gate structure, in which in a top view of the memory device, a width of the first gate structure is greater than a width of the second gate structure. The first gate spacer is on a sidewall of the first gate structure. The second gate spacer extends continuously from the first gate spacer and on a sidewall of the second gate structure, in which in the top view of the memory device, a width of the first gate spacer is less than a width of the second gate spacer.
1. A memory device, comprising:
a substrate having a P-well region and an N-well region;
a first semiconductor fin over the P-well region of the substrate;
a second semiconductor fin over the N-well region of the substrate;
a first gate structure over the P-well region of the substrate and crossing the first semiconductor fin;
a second gate structure over the N-well region of the substrate and crossing the second semiconductor fin, the first gate structure extending continuously from the second gate structure, wherein in a top view of the memory device, a width of the first gate structure is greater than a width of the second gate structure;
a first gate spacer on a sidewall of the first gate structure; and
a second gate spacer extending continuously from the first gate spacer and on a sidewall of the second gate structure, wherein in the top view of the memory device, a width of the first gate spacer is less than a width of the second gate spacer.
2. The memory device of claim 1 , wherein in the top view of the memory device, an outer sidewall of the first gate spacer farthest from the first gate structure is coterminous with an outer sidewall of the second gate spacer farthest from the second gate structure.
3. The memory device of claim 1 , wherein in the top view of the memory device, an inner sidewall of the first gate spacer closest to the first gate structure is misaligned with an inner sidewall of the second gate spacer closest to the second gate structure.
4. The memory device of claim 1 , wherein in the top view of the memory device, the first gate spacer and the second gate spacer in combination form a stepped inner sidewall profile.
5. The memory device of claim 1 , wherein in the top view of the memory device, the first gate structure contacts a longitudinal end of the second gate spacer.
6. The memory device of claim 1 , wherein in the top view of the memory device, the first gate structure and the second gate structure in combination form a stepped sidewall profile.
7. The memory device of claim 1 , wherein a bottom surface of the first gate structure is lower than a bottom surface of the first gate spacer when viewed in a cross section.
8. The memory device of claim 1 , wherein a bottom surface of the first gate structure is lower than a bottom surface of the second gate structure when viewed in a cross section.
9. A memory device, comprising:
a substrate having a P-well region and an N-well region;
an isolation structure extending along a border between the P-well region and the N-well region;
a first gate structure extending from a first side of the isolation structure within the P-well region; and
a second gate structure extending from a second side of the isolation structure within the N-well region, wherein when viewed from above, an interface between the first gate structure and the isolation structure is larger than an interface between the second gate structure and the isolation structure.
10. The memory device of claim 9 , further comprising:
a first gate spacer extending from the first side of the isolation structure and alongside the first gate structure; and
a second gate spacer from the second side of the isolation structure and alongside the second gate structure, wherein when viewed from above, an interface between the first gate spacer and the isolation structure is smaller than an interface between the second gate spacer and the isolation structure.
11. The memory device of claim 10 , further comprising:
a third gate spacer continuously extending from the second gate spacer to within another P-well region, wherein the third gate spacer and the second gate spacer in combination form a stepped inner sidewall profile when viewed from above.
12. The memory device of claim 9 , wherein the first gate structure has more layers than the second gate structure.
13. The memory device of claim 9 , further comprising:
a first semiconductor fin over the P-well region of the substrate, wherein the first gate structure crosses the first semiconductor fin, and a bottom portion of the first gate structure is embedded in the first semiconductor fin; and
a second semiconductor fin over the N-well region of the substrate, wherein the second gate structure is not embedded in the second semiconductor fin.
14. The memory device of claim 9 , wherein the first and second gate structures have a trapezoidal cross-section profile.
15. The memory device of claim 9 , further comprising:
a third gate structure continuously extending from the second gate structure to within another P-well region, the second gate structure and the third gate structure in combination form a stepped sidewall profile when viewed from above.
16. A memory device, comprising:
a substrate;
a first semiconductor fin over the substrate;
a second semiconductor fin over the substrate;
a first gate structure over the substrate and crossing the first semiconductor fin;
a second gate structure over the substrate and crossing the second semiconductor fin;
a first gate spacer on a sidewall of the first gate structure; and
a second gate spacer on a sidewall of the second gate structure, wherein in a top view of the memory device, an outer sidewall of the first gate spacer farthest from the first gate structure is coterminous with an outer sidewall of the second gate spacer farthest from the second gate structure, and an inner sidewall of the first gate spacer in contact with the first gate structure is misaligned with an inner sidewall of the second gate spacer in contact with the second gate structure, and wherein in the top view of the memory device, the first gate spacer is in contact with the second gate spacer.
17. The memory device of claim 16 , wherein in the top view of the memory device, a width of the first gate spacer is less than a width of the second gate spacer.
18. The memory device of claim 17 , wherein in the top view of the memory device, a width of the first gate structure is greater than a width of the second gate structure.
19. The memory device of claim 16 , wherein the first semiconductor fin is disposed over a P-well region of the substrate, and the second semiconductor fin is disposed over an N-well region of the substrate.
20. The memory device of claim 16 , wherein in the top view of the memory device, the first gate structure is in contact with the second gate structure.