Low power digital PDM microphone interfacing for always-on applications
An encoding technique for reducing the power of PDM microphones is disclosed. Digital MEMS microphones utilize a modulation technique called Pulse Density Modulation (PDM), where a single data line (PDMDAT) is used to convey the digital information from the microphone source to a receiver. A characteristic of PDM is that a low noise signal will produce the most transitions, a zero signal will produce an alternating bitstream of logic-1s and logic-0s, and low noise bitstreams will be rich in singleton and doubleton 1s/0s. Typically, CMOS drivers transmit the PDM bitstream signal. CMOS drivers consume power primarily when they transition, so a bitstream rich in singletons and doubletons will increase power consumption. Differential encoding with an XNOR function is used as a singleton-suppression encoder, and a differential encoding with an XOR function is used as a doubleton-suppression encoder. In some embodiments, such as a dual PDM microphone configuration, the microphones alternate sending data on the rising (transition to logic-1) and falling (transition to logic-0) edges of PDMCLK. In other embodiments, a Voice Activity Detection (VAD) function may be added. In some other embodiments, a suppressed clock pulse duration modulator may be added.
1. A device comprising:
a clock source configured to distribute a series of clock pulses, wherein:
each clock pulse comprises a first phase and a second phase; and
a first microphone, comprising:
a first transducer,
a first sigma-delta modulator,
a first singleton-suppression encoder,
a first doubleton-suppression encoder, and
a first output driver.
2. The device of claim 1 , wherein:
the first transducer is configured to convert sound in a first acoustic environment to a first analog signal,
the first sigma-delta modulator is configured to convert the first analog signal to a first pulse density modulated bitstream, each bit of the bitstream comprising a symbol,
the first singleton-suppression encoder is configured to convert the first pulse density modulated bitstream to a first singleton-suppressed bitstream, each bit of the bitstream comprising a symbol,
the first doubleton-suppression encoder is configured to convert the first singleton-suppressed bitstream to a first doubleton-suppressed bitstream, each bit of the bitstream comprising a symbol, and
the first output driver is configured to transmit the first doubleton-suppressed bitstream as a first output bitstream, each bit of the bitstream comprising a symbol.
3. The device of claim 2 , wherein the first singleton-suppression encoder performs an exclusive-NOR (XNOR) function on the current input symbol and the previous input symbol to generate an output symbol.
4. The device of claim 3 , wherein the first second doubleton-suppression encoder performs an exclusive-OOR (XOR) function on the current input symbol and the previous input symbol to generate an output symbol.
5. The device of claim 4 , further comprising:
a second microphone, comprising:
a second transducer,
a second sigma-delta modulator,
a second singleton-suppression encoder,
a second doubleton-suppression encoder, and
a second output driver.
6. The device of claim 5 , wherein:
the second transducer is configured to convert sound in a second acoustic environment to a second analog signal,
the second sigma-delta modulator is configured to convert the second analog signal to a second pulse density modulated bitstream, each bit of the bitstream comprising a symbol,
the second singleton-suppression encoder is configured to convert the second pulse density modulated bitstream to a second singleton-suppressed bitstream, each bit of the bitstream comprising a symbol,
the second doubleton-suppression encoder is configured to convert the second singleton-suppressed bitstream to a second doubleton-suppressed bitstream, each bit of the bitstream comprising a symbol, and
the second output driver is configured to transmit the second doubleton-suppressed bitstream as a second output bitstream, each bit of the bitstream comprising a symbol.
7. The device of claim 6 , further comprising:
a device output; and
a synchronization logic, wherein:
the first output driver further comprises:
a first output driver data input coupled to the first doubleton-suppression encoder,
a first output driver enable input coupled to the synchronization logic, and
a first output driver data output coupled to the device output;
the second output driver further comprises:
a second output driver data input coupled to the second doubleton-suppression encoder,
a second output driver enable input coupled to the synchronization logic, and
a second output driver data coupled to the device output.
8. The device of claim 7 , wherein:
the synchronization logic is configured to:
enable the first output driver and disable the second output driver during the first phase of the clock; and
disable the first output driver and enable the second output driver during the second phase of the clock.
9. The device of claim 4 , further comprising:
a Voice Activity Detection (VAD) logic, wherein:
if the VAD logic detects acoustic energy above a predefined threshold, then the output bitstream is enabled, and
if the VAD logic detects acoustic energy below a predefined threshold, then the output bitstream is disabled.
10. The device of claim 4 , further comprising a suppressed carrier pulse width modulation logic coupled between the first doubleton-suppression encoder and the first output driver.