Integer matrix multiplication engine using pipelining

1. A processor-implemented method comprising:

obtaining a first integer matrix with dimensions m×k and a second integer matrix with dimensions k×n for matrix multiplication within a processor, wherein the first integer matrix and the second integer matrix employ a two's complement variable radix point data representation;

distilling the first integer matrix and the second integer matrix into (j×j) submatrices;

configuring dynamically both a variable radix point format and an initial value for an accumulator register;

executing multiply-accumulate (MAC) operations in a pipelined architecture on the (j×j) submatrices of the first integer matrix and the second integer matrix, wherein a third variable radix point format is configured for the result; and

using the executed MAC operations to process data in a data-flow architecture.

2. The method of claim 1 further comprising configuring dynamically a first variable radix point format for the first integer matrix and a second variable radix point format for the second integer matrix.

3. The method of claim 2 wherein the first variable radix point format and the second variable radix point format comprise a 16-bit data type.

4. The method of claim 2 wherein the first variable radix point format and the second variable radix point format comprise a 4-bit primitive data type.

5. The method of claim 2 wherein the first variable radix point format and the second variable radix point format comprise an 8-bit primitive data type.

6. The method of claim 1 further comprising outputting results of the matrix multiplication to a storage element, wherein the outputting takes an additional (m×k) cycles.

7. The method of claim 1 wherein the first integer matrix and the second integer matrix comprise subsections of an o-dimensional tensor, wherein o is greater than 2.

8. The method of claim 1 wherein each multiply-accumulate (MAC) unit used for matrix multiplication in the processor is configured to have an accumulator depth of m.

9. The method of claim 1 further comprising pipelining input elements to multiply-accumulate (MAC) units used for matrix multiplication in the processor through two input registers.

10. The method of claim 1 wherein performing N multiply-accumulate (MAC) operations in parallel reduces an amount of time taken to perform the N MAC operations from an order of magnitude of N 3 to an order of magnitude of N 2 .

11. The method of claim 1 further comprising adding one or more idle or no operation (NOP) cycles after completion of a matrix multiply operation before starting a next matrix multiply operation.

12. The method of claim 1 wherein a processor and memory subsystem is allocated as part of one or more clusters within a reconfigurable fabric to implement MAC units.

13. The method of claim 12 , wherein each cluster of the one or more clusters within the reconfigurable fabric is controlled by one or more circular buffers.

14. The method of claim 13 , wherein the one or more circular buffers are statically scheduled.

15. The method of claim 12 , wherein each cluster of the one or more clusters within the reconfigurable fabric comprises process elements, switching elements, or storage elements.

16. The method of claim 1 , wherein the data-flow architecture implements machine learning.

17. The method of claim 1 , wherein the machine learning utilizes one or more convolutional neural networks.

18. The method of claim 1 , wherein executing multiply-accumulate operations in a pipelined architecture is accomplished using systolic data flow.

19. One or more non-transitory computer readable media embodying one or more instructions that are operable when executing by one or more processors to perform operations of:

obtaining a first integer matrix with dimensions m×k and a second integer matrix with dimensions k×n for matrix multiplication within a processor, wherein the first integer matrix and the second integer matrix employ a two's complement variable radix point data representation;

distilling the first integer matrix and the second integer matrix into (j×j) submatrices;

configuring dynamically both a variable radix point format and an initial value for an accumulator register;

executing multiply-accumulate operations in a pipelined architecture—on the (j×j) submatrices of the first integer matrix and the second integer matrix, wherein a third variable radix point format is configured for the result; and

using the executed MAC operations to process data in a data-flow architecture.

20. A system comprising: a memory which stores instructions; and

one or more processors coupled to the memory wherein the one or more processors, when executing the instructions, are configured to:

obtain a first integer matrix with dimensions m×k and a second integer matrix with dimensions k×n for matrix multiplication within a processor, wherein the first integer matrix and the second integer matrix employ a two's complement variable radix point data representation;

distill the first integer matrix and the second integer matrix into (j×j) submatrices;

configure dynamically both a variable radix point format and an initial value for an accumulator register; and

execute multiply-accumulate operations in a pipelined architecture on the (j×j) submatrices of the first integer matrix and the second integer matrix, wherein a third variable radix point format is configured for the result; and

use the executed MAC operations to process data in a data-flow architecture.