Radio frequency chips having waveform generators for self-testing
Embodiments of apparatus and method for generating waveforms for self-testing of radio frequency (RF) chips are disclosed. In an example, an RF chip includes an RF front-end and a digital front-end. The digital front-end includes an inverse fast Fourier transform (IFFT) module configured to generate at least one M-point IFFT sample, where M is a positive integer, and an IFFT sample transformation module configured to generate an L-point IFFT testing signal based on the at least one M-point IFFT sample. L is a positive integer greater than M and the L-point IFFT testing signal is configured to test a function of the RF chip.
1. A radio frequency (RF) chip comprising:
a RF front-end; and
a digital front-end comprising:
a waveform generator configured to;
generate at least one M-point inverse fast Fourier transform (IFFT) sample, where M is a positive integer; and
generate an L-point IFFT testing signal based on the at least one M-point IFFT sample, where L is a positive integer greater than M,
wherein the L-point IFFT testing signal is configured to test a function of the RF chip.
2. The RF chip of claim 1 , wherein the waveform generator is further configured to generate an input IFFT sample based on a resource block (RB) configuration and a pseudo-random binary sequence (PRBS).
3. The RF chip of claim 2 , wherein to generate the at least one M-point IFFT sample, the waveform generator is configured to generate the at least one M-point IFFT sample based on the input IFFT sample.
4. The RF chip of claim 3 , wherein the waveform generator further comprises N readers each configured to generate an output IFFT sample based on one of the at least one M-point IFFT sample, where N is a positive integer, wherein each of the output IFFT samples of the N readers is different from one another.
5. The RF chip of claim 4 , wherein the waveform generator further comprises:
N frequency shifters, each of the N frequency shifters being configured to shift a central frequency of the output IFFT sample generated by a respective reader of the N readers to separate the central frequencies of the output IFFT samples of the N readers; and
an adder configured to combine the shifted output IFFT samples to generate the L-point IFFT testing signal.
6. The RF chip of claim 5 , wherein the waveform generator further comprises at least one buffer configured to store the at least one M-point IFFT sample.
7. The RF chip of claim 6 , wherein the waveform generator further comprises:
a pair of ping-pong buffers configured to:
store, in a first buffer of the pair of ping-pong buffers, a first M-point IFFT sample; and
feed, by a second buffer of the pair of ping-pong buffers, a second M-point IFFT sample stored in the second buffer to the N readers, wherein roles of the first buffer and the second buffer are dynamically changed.
8. The RF chip of claim 6 , wherein each of the N readers is a symmetric reader, and to generate the output IFFT sample, each of the N symmetric readers is further configured to:
read the one of the at least one M-point IFFT sample from the at least one buffer; and
transform the one of the at least one M-point IFFT sample read from the at least one buffer to generate the output IFFT sample, wherein each algorithm applied by a respective symmetric reader to transform the one of the at least one M-point IFFT sample is different from one another.
9. The RF chip of claim 5 , wherein the waveform generator is configured to generate N M-point IFFT samples that are different from one another, and each of the N readers is a circular reader.
10. The RF chip of claim 9 , wherein the waveform generator further comprises:
N buffers, each configured to store one of the N M-point IFFT samples; and
to generate the output IFFT sample, each of the N circular readers is configured to:
read the one M-point IFFT sample stored in a respective buffer of the N buffers; and
output the one M-point IFFT sample to generate the output IFFT sample.
11. The RF chip of claim 1 , wherein the L-point IFFT testing signal comprises a 4096-point IFFT cyclic prefix-orthogonal frequency division multiplexing (CP-OFDM) waveform.
12. The RF chip of claim 5 , wherein L=4096, M is a factor of 4096, and M×N=4096.
13. A radio frequency (RF) chip comprising a digital front-end, the digital front-end comprising:
a waveform generator configured to generate at least one M-point inverse fast Fourier transform (IFFT) sample based on a resource block (RB) configuration and a pseudo-random binary sequence (PRBS), where M is a positive integer;
wherein the waveform generator comprises:
N readers, each of the N readers being configured to generate an output IFFT sample based on one of the at least one M-point IFFT sample, wherein each of the generated N output IFFT samples is different from one another, where N is a positive integer;
N frequency shifters, each of the N frequency shifters being configured to shift a central frequency of the output IFFT sample generated by a respective reader of the N readers to separate the central frequencies of the output IFFT samples of the N readers; and
an adder configured to combine the shifted N output IFFT samples to generate an L-point IFFT testing signal, where L is a positive integer greater than M, wherein M×N=L.
14. The RF chip of claim 13 , wherein the waveform generator further comprises at least one buffer configured to store the at least one M-point IFFT sample.
15. The RF chip of claim 14 , wherein the waveform generator further comprises:
a pair of ping-pong buffers configured to:
store, in a first buffer of the pair of ping-pong buffers, a first M-point IFFT sample; and
feed, by a second buffer of the pair of ping-pong buffers, a second M-point IFFT sample stored in the second buffer to one of the N readers, wherein roles of the first buffer and the second buffer are dynamically changed.
16. The RF chip of claim 14 , wherein each of the N readers is a symmetric reader, and to generate the output IFFT sample, each of the N symmetric readers is further configured to:
read the one of the at least one M-point IFFT sample from the at least one buffer; and
transform the one of the at least one M-point IFFT sample read from the at least one buffer to generate the output IFFT sample, wherein each algorithm applied by a respective symmetric reader to transform the one of the at least one M-point IFFT sample is different from one another.
17. The RF chip of claim 13 , wherein the waveform generator is configured to generate N M-point IFFT samples that are different from one another, and each of the N readers is a circular reader.
18. The RF chip of claim 17 , wherein the digital front-end further comprises:
N buffers, each configured to store one of the N M-point IFFT samples; and
to generate the output IFFT sample, each of the N circular readers is configured to:
read the one M-point IFFT sample stored in a respective buffer of the N buffers; and
output the one M-point IFFT sample to generate the output IFFT sample.
19. A method for self-testing of a radio frequency (RF) chip, the method comprising:
generating at least one M-point inverse fast Fourier transform (IFFT) sample based on a resource block (RB) configuration and a pseudo-random binary sequence (PRBS), where M is a positive integer;
generating N output IFFT samples based on the at least one M-point IFFT sample, where N is a positive integer, wherein each of the generated N output IFFT samples is different from one another;
shifting a central frequency of each of the N output IFFT samples to separate the central frequencies of the N output IFFT samples; and
combining the shifted N output IFFT samples to generate an L-point IFFT testing signal configured to test a function of the RF chip, where L is a positive integer greater than M, wherein M×N=L.
20. The method of claim 19 , wherein the L-point IFFT testing signal comprises a 4096-point IFFT cyclic prefix-orthogonal frequency division multiplexing (CP-OFDM) waveform.