Method for reducing parasitic junction field effect transistor resistance
A method for reducing parasitic junction field effect transistor resistance, applicable to a high power device having a semiconductor substrate layer, is provided, including providing a plurality of hard masks on a top surface of the semiconductor substrate layer. Each hard mask has a bottom plane and a tilt sidewall such that an acute angle is formed there in between. A body ion implantation process is subsequently performed, so a body region is formed between two adjacent hard masks. The body region has an upper and a lower surface. A width of the upper surface is greater than that of the lower surface. Therefore, the present invention achieves to control a parasitic JFET region characterized by having a wider bottom and a narrower top, thereby reducing its resistance thereof. Meanwhile, since a bottom angle of the body region is increased, breakdown voltage of the device is increased as well.
1 . A method for reducing parasitic junction field effect transistor resistance, which is applicable to a high power device including a semiconductor substrate layer, the method comprising:
providing a plurality of hard masks on a top surface of the semiconductor substrate layer, wherein each of the plurality of hard masks includes a bottom plane and a tilt sidewall, and an acute angle is formed between the tilt sidewall and the bottom plane; and
performing a body ion implantation process, such that at least one body region is formed between adjacent two of the plurality of hard masks in the semiconductor substrate layer, the at least one body region has an upper surface and a lower surface, and a width of the upper surface is greater than that of the lower surface, wherein between the upper surface and the lower surface of the body region is a connecting sidewall, both the connecting sidewall of the body region and the tilt sidewall of the hard mask have a sloped sidewall, and a slope of the connecting sidewall of the body region is the same as the slope of the tilt sidewall of the hard mask.
2 . The method according to claim 1 , wherein when there are at least two of the body regions formed in the semiconductor substrate layer, a parasitic junction field effect transistor region is formed between two of the body regions, the parasitic junction field effect transistor region has an upper width and a lower width, and the lower width is greater than the upper width.
3 . The method according to claim 1 , wherein the plurality of hard masks are formed by applying a lithography process to a barrier layer, and the barrier layer is made of silicon dioxide, silicon nitride, or polysilicon.
4 . The method according to claim 3 , wherein a thickness of the barrier layer is between 0.5 μm and 3 μm.
5 . The method according to claim 1 , wherein the acute angle is between 30 degrees and 85 degrees.
6 . The method according to claim 1 , wherein the body ion implantation process is performed by using ions such as boron (B), aluminum (Al), phosphorus (P), or nitrogen (N).
7 . The method according to claim 1 , wherein an ion implantation dose of the body ion implantation process is between 1012 cm-2 and 1014 cm-2.
8 . The method according to claim 1 , wherein an ion implantation energy of the body ion implantation process is between 10 keV and 2 MeV.
9 . The method according to claim 1 , wherein one of the plurality of hard masks is formed as a trapezoid or a triangle.
10 . The method according to claim 1 , after the body region is formed, further comprising:
removing the plurality of hard masks, and growing a field oxide layer;
applying a lithography process to the field oxide layer to define a gate region;
forming a gate oxide layer in the gate region;
forming a gate conductive layer on the gate oxide layer and further depositing a dielectric layer on the gate conductive layer; and
forming at least one contact window which extends through the dielectric layer, and electrically connected to the semiconductor substrate layer of the high power device for providing electrical paths.
11 . The method according to claim 10 , wherein in the step of forming the gate conductive layer, further comprising:
using a low-pressure chemical vapor deposition (LPCVD) process to deposit a polysilicon; and
using an etch back process to etch back the polysilicon, so as to form the gate conductive layer.
12 . The method according to claim 1 , wherein the semiconductor substrate layer of the high power device is made of a semiconductor material, such as silicon (Si), silicon carbide (SiC), gallium oxide (Ga 2 O 3 ), aluminum nitride (AlN), or diamond.
13 . The method according to claim 1 , wherein the high power device is a Vertical Double Diffused Metal Oxide Semiconductor Field Effect Transistor (VDMOSFET), or an Insulated Gate Bipolar Transistor (IGBT).
14 . The method according to claim 1 , wherein the semiconductor substrate layer of the high power device comprises an N-type semiconductor substrate, an N-type epitaxial layer, a first N-type heavily doped region, a second N-type heavily doped region, a first P-type heavily doped region, a second P-type heavily doped region, and at least one floating guard ring, the N-type epitaxial layer is disposed on the N-type semiconductor substrate, the first P-type heavily doped region is disposed adjacent to the first N-type heavily doped region, and the first P-type heavily doped region and the first N-type heavily doped region are commonly disposed in the N-type epitaxial layer, the second P-type heavily doped region is disposed adjacent to the second N-type heavily doped region, and the second P-type heavily doped region and the second N-type heavily doped region are commonly disposed in the N-type epitaxial layer, the at least one floating guard ring is formed at a termination outside the first P-type heavily doped region or the second P-type heavily doped region.
15 . The method according to claim 14 , wherein the first N-type heavily doped region and the second N-type heavily doped region are formed by using a source ion implantation in the N-type epitaxial layer.
16 . The method according to claim 14 , wherein the N-type semiconductor substrate is an N-type silicon carbide (SiC) substrate.