Shift register, gate driving circuit, display apparatus and driving method

1. A shift register, comprising:

a first input sub-circuit, configured to receive a first input signal from a first input terminal and output a blanking output control signal;

a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal, wherein the second input signal is a turn-on signal of a high level; and

an output sub-circuit, configured to output a composite output signal via an output terminal under control of a first node, the composite output signal including a display output signal outputted in a display period of time and a blanking output signal outputted in a blanking period of time which are independent of each other,

wherein the second input sub-circuit comprises a first display input transistor and a second display input transistor, and an electrode of the first display input transistor is connected to an electrode of the second display input transistor,

wherein a first electrode of the first display input transistor is connected to a high level signal line, a control electrode of the first display input transistor is connected to a display input signal line or an output terminal of another shift register, and a second electrode of the first display input transistor is connected to an electrode of the second display input transistor.

2. The shift register according to claim 1 , wherein a first electrode of the second display input transistor and a control electrode of the second display input transistor are connected with each other.

3. The shift register according to claim 1 , wherein a first electrode of the second display input transistor and a control electrode of the second display input transistor are configured to receive the turn-on signal of a high level, and a second electrode of the second display input transistor are connected to a first pull-up node.

4. The shift register according to claim 1 , further comprising: a display reset sub-circuit, configured to reset the first node under control of a display reset control signal.

5. The shift register according to claim 4 , wherein the display reset sub-circuit comprises a display reset transistor, having a first electrode connected to the first node, a control electrode connected to a display reset control terminal, and a second electrode connected to a display reset signal line.

6. The shift register according to claim 1 , wherein the output sub-circuit comprises at least one shift signal output terminal and at least one pixel signal output terminal.

7. The shift register according to claim 6 , further comprising:

a pull-down control sub-circuit, configured to control a potential of a pull-down node according to the first node; and

a pull-down sub-circuit, configured to pull down the first node and the output terminal to a non-operating potential under control of the pull-down node.

8. The shift register according to claim 7 , wherein the pull-down sub-circuit comprises a first pull-down transistor having an electrode connected to a first signal line, and a second pull-down transistor having an electrode connected to a second signal line, the first signal line and the second signal line are different signal line.

9. The shift register according to claim 8 , wherein the pull-down control sub-circuit comprises a pull-down control transistor having an electrode connected to the first signal line.

10. The shift register according to claim 1 , wherein the first input sub-circuit comprises:

a charging sub-circuit, configured to input the first input signal to a blanking pull-up control node according to the first input signal;

a storing sub-circuit, having a terminal connected to the blanking pull-up control node, configured to store a blanking pull-up control signal according to the first input signal; and

an isolating sub-circuit, configured to input the blanking output control signal to the first node according to the blanking pull-up control signal in a blanking period of time of a frame.

11. The shift register according to claim 10 , wherein the charging sub-circuit comprises a charging transistor, having a first electrode and/or control electrode connected to the first input terminal, and a second electrode connected to the blanking pull-up control node; and

the storing sub-circuit comprises a first capacitor, having a first terminal connected to the blanking pull-up control node; and the isolating sub-circuit comprises a first isolating transistor, wherein a control terminal of the first isolating transistor is connected to the blanking pull-up control node, and an electrode of the first isolating transistor is connected to the output terminal of the first input sub-circuit.

12. The shift register according to claim 11 , wherein a first terminal of the first capacitor is connected to the blanking pull-up control node, and a second terminal of the first capacitor is configured to receive a constant voltage value of a first power source signal.

13. The shift register according to claim 11 , wherein another electrode of the first isolating transistor is connected to a terminal of the first capacitor for receiving the same signal.

14. The shift register according to claim 10 , wherein the output sub-circuit comprises an output transistor and an output capacitor, wherein a first electrode of the output transistor is connected to an output clock signal line, a second electrode of the output transistor is connected to the output terminal, a control electrode of the output transistor is connected to the first node, a first terminal of the output capacitor is connected to the first node, and a second terminal of the output capacitor is connected the output terminal.

15. A driving method applicable to the shift register according to claim 1 , comprising:

a display period of time of a frame, comprising

in a first control phase, inputting, by the first input sub-circuit, a first pull-up signal to the first node;

in a first output phase, outputting, by the output sub-circuit, a first output signal under control of the first node;

a blanking period of time of the frame, comprising

in a second control phase, inputting, by the second input sub-circuit, a second pull-up signal to the first node;

in a second output phase, outputting, by an output sub-circuit, a second output signal under control of the first node.

16. A shift register comprising:

a first input sub-circuit, configured to receive a first input signal from a first input terminal and output a blanking output control signal;

a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal, wherein the second input signal is a turn-on signal of a high level;

an output sub-circuit, configured to output a composite output signal via an output terminal under control of a first node, the composite output signal including a display output signal outputted in a display period of time and a blanking output signal outputted in a blanking period of time which are independent of each other;

a display reset sub-circuit, configured to reset the first node under control of a display reset control signal;

a pull-down control sub-circuit, configured to control a potential of a pull-down node according to the first node; and

a pull-down sub-circuit, configured to pull down the first node and the output terminal to a non-operating potential under control of the pull-down node, and comprising a pull-down control transistor having an electrode connected to a first signal line;

wherein,

the first input sub-circuit comprises a charging sub-circuit, a storing sub-circuit, and an isolating sub-circuit, wherein

the charging sub-circuit comprises a charging transistor, having a first electrode and/or control electrode connected to the first input terminal, and a second electrode connected to a blanking pull-up control node;

the storing sub-circuit comprises a first capacitor, having a first terminal connected to the blanking pull-up control node; and

the isolating sub-circuit comprises a first isolating transistor, wherein a control terminal of the first isolating transistor is connected to the blanking pull-up control node, and an electrode of the first isolating transistor is connected to the output terminal of the first input sub-circuit;

the second input sub-circuit comprises:

a display input transistor, wherein a first electrode of the display input transistor and a control electrode of the display input transistor are connected with each other, and the second electrode of the display input transistor is connected to a first pull-up node;

the output sub-circuit comprises:

a first output transistor, wherein a first electrode of the first output transistor is connected to a fourth clock signal line, a second electrode of the first output transistor is connected to a first output terminal, and a control electrode of the first output transistor is connected to the first pull-up node;

a second output transistor, wherein a first electrode of the second output transistor is connected to the fourth clock signal line, a second electrode of the second output transistor is connected to a second output terminal, and a control electrode of the second output transistor is connected to the first pull-up node; and

an output capacitor, wherein a first electrode of the output capacitor is connected to the first pull-up node, and a second electrode of the output capacitor is connected to the first output terminal.