Granted Patent B2

US 12,558,034 · App. 17/882,419 · Granted Feb 24, 2026

Inventors: Cameron Mahon (Hunt Valley, MD); Curt Labelle (Hunt Valley, MD)

Assignee: SAFEOP SURGICAL, INC.

A61B5/24A61B5/311A61B5/377A61B5/388A61B5/4041A61B5/7217A61B5/725A61N1/0456A61N1/20A61B2017/00026

Abstract

Claims (31)

1 . An evoked potential detection device comprising:

a housing;

at least one memory storing instructions for stimulating a peripheral nerve and recording one or more evoked potentials detected signals;

at least one data processor configured to initiate the stimulating and the recording;

an unshielded wire for detecting electromagnetic waves, wherein at least a portion of the unshielded wire which extends beyond the housing; and

an amplifier system, comprising:

a first signal pathway, and a second signal pathway coupled to the unshielded wire,

wherein the one or more evoked potentials comprises a target signal and high frequency interference,

wherein the first signal pathway is configured to amplify the target signal, and

wherein the second signal pathway is configured to detect the high frequency interference.

2 . The evoked potential detection device of claim 1 , wherein the first signal pathway comprises, in order:

a low pass filter,

an amplifier,

an analog to digital converter, and

a microprocessor.

3 . The evoked potential detection device of claim 2 , wherein the second signal pathway comprises:

a band pass filter or high pass filter electrically coupled to a radiofrequency detector,

a comparator,

a digital to analog converter, and

the microprocessor of the first signal pathway;

wherein the comparator is configured to compare a first amplitude of a first signal entering from a first leg and a second amplitude of a second signal entering from a second leg, the first leg of the comparator being electrically coupled to an output from the radiofrequency detector, and the second leg being electrically coupled via the digital to analog converter to an output from the microprocessor.

4 . The evoked potential detection device of claim 3 , wherein the microprocessor is electrically coupled to an output from the comparator and is configured to detect high frequency interference within the one or more evoked potentials when the first amplitude is greater than the second amplitude.

5 . The evoked potential detection device of claim 4 , further comprising a control line electrically connecting the microprocessor to the amplifier, wherein the control line is configured to deliver an interrupt signal to the amplifier upon detection of high frequency interference.

6 . The evoked potential detection device of claim 5 , wherein the amplifier is configured to, upon detection of the high frequency interference, suspend operation until transmission of the interrupt signal ceases.

7 . The evoked potential detection device of claim 3 , further comprising one or more low pass filters positioned between the comparator and the microprocessor.

8 . The evoked potential detection device of claim 3 , wherein the band pass filter of the second signal pathway comprises one or more inductors, capacitors, or a combination thereof, configured to pass a frequency band of interest while eliminating signals outside the frequency band of interest.

9 . The evoked potential detection device of claim 8 , wherein the frequency band of interest is 200 kHz to 6 MHz.

10 . The evoked potential detection device of claim 3 , wherein the radiofrequency detector comprises an ultrafast diode, a capacitor connected to ground, and a parallel shunt resistor connected to ground.

11 . The evoked potential detection device of claim 1 , wherein the evoked potential detection device is configured to temporarily suspend data acquisition upon detection of the high frequency interference.

12 . The evoked potential detection device of claim 1 , wherein the at least one data processor of the evoked potential detection device, upon detection of the high frequency interference, is configured to perform one or more steps to suspend signal acquisition.

13 . The evoked potential detection device of claim 12 , wherein the at least one data processor is configured to suspend acquisition and storage of digital data by a microprocessor, wherein the digital data is received from an analog to digital converter of the first signal pathway, and wherein the digital data is a digitized first detected signal.

Assignments (6)

Continuity (4)

References Cited (267)