Memory device having shared read/write access line for 2-transistor vertical memory cell
Some embodiments include apparatuses and methods operating the apparatuses. One of the apparatuses includes a first data line located over a substrate, a second data line located over the first data line, a third data line located over the second data line and electrically separated from the first and second data lines, and a memory cell coupled to the first, second, and third data lines. The memory cell includes a first material between the first and second data lines and electrically coupled to the first and second data lines; a second material located over the first data line and the first material, the second material electrically separated from the first material and electrically coupled to the third data line; and a memory element electrically coupled to the second material and electrically separated from the first material and first and second data lines.
1. A method comprising:
applying a first voltage to an access line of a volatile memory device, the access line controlling a first transistor and a second transistor of a memory cell of the volatile memory device during an operation of storing information in a memory element of the memory cell, the memory element directly coupled to a channel region of the second transistor, the first and second transistors having different threshold voltages, the volatile memory device including a first data line coupled to the first transistor, a second data line coupled to the first transistor, and a third data line coupled to the second transistor;
placing each of the first and second data lines in a float condition during the operation; and
applying a second voltage to the third data line during the operation.
2. The method of claim 1 , wherein the second voltage is less than the first voltage.
3. The method of claim 1 , wherein the second voltage is equal to the first voltage.
4. The method of claim 1 , wherein the second voltage is greater than the first voltage.
5. The method of claim 1 , further comprising:
applying a third voltage to the access line during an additional operation of reading information from the memory cell; and
applying different voltages to the first, second, and third data lines during the additional operation.
6. A method comprising:
applying a first voltage to an access line of a memory device during an operation of reading information from a memory element of a memory cell of the memory device, the memory cell including a first transistor and a second transistor coupled to the access line, the memory element coupled to a channel region of the second transistor, the first and second transistors having different threshold voltages, the memory device including a first data line coupled to the first transistor, a second data line coupled to the first transistor, and a third data line coupled to the second transistor;
applying a second voltage to the first data line during the operation;
applying a third voltage to the second data line during the operation; and
applying a fourth voltage to the third data line during the operation.
7. The method of claim 6 , wherein the second voltage is less than the first voltage.
8. The method of claim 6 , wherein the second voltage includes ground potential.
9. The method of claim 6 , wherein the third voltage is equal to the first voltage.
10. The method of claim 6 , wherein the third voltage is greater than the second voltage.
11. The method of claim 6 , wherein the third voltage is greater than the fourth voltage.
12. The method of claim 6 , wherein the fourth voltage includes a positive voltage.
13. A method comprising:
applying a first voltage to an access line of a memory device during an operation in a first memory cell of the memory device, the first memory cell including a first transistor coupled to the access line and a second transistor coupled to the access line, the first and second transistors having different threshold voltages;
the memory device including a first data line coupled to the first transistor, a second data line coupled to the first transistor, and a third data line coupled to the second transistor;
the memory device including a second memory cell sharing the access line with the first memory cell, the second memory cell including a first additional transistor coupled to the access line and a second additional transistor coupled to the access line;
the memory device including a first additional data line coupled to the first additional transistor, a second additional data line coupled to the first additional transistor, and a third additional data line coupled to the second additional transistor; and
placing the first additional data line in a float condition during the operation.
14. The method of claim 13 , further comprising:
placing the second additional data line in a float condition during the operation.
15. The method of claim 13 , further comprising:
applying a second voltage to the first data line during the operation;
applying a third voltage to the second data line during the operation; and
applying a fourth voltage to the third data line during the operation.
16. The method of claim 15 , wherein the second voltage is less than the first voltage.
17. The method of claim 15 , wherein the second voltage includes ground potential.
18. The method of claim 13 , wherein the third voltage is greater than the second voltage.
19. The method of claim 13 , wherein the third voltage is greater than the fourth voltage.
20. The method of claim 13 , further comprising:
applying a second voltage to the third data line during the operation; and
placing at least one of the first and second data lines in a float condition during the operation.