Granted Patent B2

US 12,386,742 · App. 17/888,398 · Granted Aug 12, 2025

Inventors: Anirban Ray (Santa Clara, CA); Parag R. Maharana (Dublin, CA); Gurpreet Anand (Pleasanton, CA)

Assignee: Micron Technology, Inc.

G06F12/0802G06F9/5077G06F12/0238G06F16/972

Abstract

Claims (53)

1. A computing system, comprising:

at least one bus;

a plurality of memory components, comprising first memory and second memory, wherein the first memory and the second memory have different speeds when accessed via the at least one bus;

a processing device, operatively coupled with the plurality of memory components through the at least one bus;

wherein the computing system further comprises a memory virtualizer operatively to:

store an address map between first addresses used by the processing device to access memory and second addresses used to access the first memory and the second memory;

monitor usages of the first memory and the second memory, and train a self-learning prediction engine to generate a prediction associated with a use of the first memory and the second memory; and

adjust the address map based on the prediction to improve speed of the processing device in memory access involving the first memory and the second memory; and

swap data content in the first memory and the second memory according to adjustments to the address map;

wherein the adjusting of the address map based on the prediction are shielded from an application, virtual machine, or a combination thereof, associated with a request to access a memory location currently in the second memory.

2. The computing system of claim 1 , wherein the first memory is faster than the second memory; and the processing device accesses the second memory over the at least one bus without accessing the first memory for a portion of memory access requests in the computing system.

3. The computing system of claim 1 , wherein the first memory is faster than the second memory; and the first memory and the second memory share a common physical host interface to the bus.

4. The computing system of claim 3 , wherein the first memory and the second memory are disposed in a same memory module.

5. The computing system of claim 4 , wherein the bus is a memory bus; and the memory module is a dual in-line memory module (DIMM).

6. The computing system of claim 5 , wherein the memory module includes a controller that implements at least in part the memory virtualizer.

7. The computing system of claim 6 , wherein in response to a request to access a memory location currently in the second memory, the memory virtualizer instructs the controller to swap data content between a portion of the first memory and a portion of the second memory, in response to a determination that data content in the portion of the first memory is accessed less frequently than the portion of the second memory.

8. The computing system of claim 7 , wherein swapping of the data content between the portion of the first memory and the portion of the second memory is performed within the memory module without going through the bus.

9. The computing system of claim 7 , wherein the swapping of the data content between the portion of the first memory and the portion of the second memory is performed after accessing the memory location in the second memory.

10. The computing system of claim 5 , wherein the memory virtualizer comprises a device driver of the memory module running in the processing device.

11. The computing system of claim 10 , wherein the device driver runs in the processing device to:

receive an address of a memory access request to be made by the processing device;

convert the address to a converted address based on the address map; and

make the memory access request on the bus according to the converted address.

12. The computing system of claim 10 , wherein the memory virtualizer adjusts the address map to place first data in the first memory and second data in the second memory based on a determination that first data is accessed more frequently in a time period than the second data.

13. The computing system of claim 1 , wherein the first memory and the second memory are in a same memory module; and at least a portion of the second memory is not directly addressable on the at least one bus.

14. The computing system of claim 13 , wherein the first memory is volatile dynamic random-access memory and the second memory is non-volatile cross-point memory.

15. The computing system of claim 1 , wherein the first memory and the second memory are in separate memory modules that are coupled to a central processing unit via a same memory bus.

16. The computing system of claim 1 , wherein the first memory and the second memory are in separate memory systems that are coupled to a central processing unit via separate communication channels.

17. A method, comprising:

providing a plurality of memory components on at least one bus coupled to a processing device, the plurality of memory components comprising first memory and second memory, wherein the first memory and the second memory have different speeds when accessed via the at least one bus;

storing an address map between first addresses used by the processing device to access memory and second addresses used to access the first memory and the second memory;

monitoring usages of the first memory and the second memory and training a self-learning prediction engine to predict a use of the first memory and the second memory; and

adjusting the address map based on the prediction to improve speed of the processing device in memory access involving the first memory and the second memory; and

swapping data content in the first memory and the second memory according to adjustments to the address map;

wherein the adjusting of the address map based on the prediction, are shielded from an application, virtual machine, or a combination thereof, associated with a request to access a memory location currently in the second memory.

18. The method of claim 17 , further comprising

generating, by a hypervisor, information that is used to predict the usages of the first memory and the second memory.

19. The method of claim 18 , wherein the information comprises at least one of:

a sequence of pages being used in a period of time;

instances of requests to load pages from the second memory to the first memory;

content attributes of the pages loaded from the second memory to the first memory;

ownership attributes of the pages loaded from the second memory to the first memory;

identifications of users of the pages loaded from the second memory to the first memory;

identifications of applications loaded from the second memory to the first memory;

an identification of pages that are accessed in a sequential mode in a virtual machine;

an identification of pages that are accessed in a sequential mode in a user account; and

an identification of page accesses that are in a steady state.

20. A non-transitory computer storage medium storing instructions which, when executed by a computing system having first memory, and second memory provided on at least one bus coupled to a processing device, cause the computing system to perform a method, the method comprising:

storing an address map between first addresses used by the processing device to access memory and second addresses used to access the first memory and the second memory;

monitoring usages of the first memory and the second memory and training a self-learning prediction engine to generate a prediction associated with a use of the first memory and the second memory;

adjusting the address map based on the prediction to improve speed of the processing device in memory access involving the first memory and the second memory; and

swapping data content in the first memory and the second memory according to adjustments to the address map;

wherein the adjusting of the address map based on the prediction, are shielded from an application, virtual machine, or a combination thereof, associated with a request to access a memory location currently in the second memory.

Assignments (1)

Continuity (3)

References Cited (242)