Shadow cache for securing conditional speculative instruction execution

1. A computing device, comprising:

a processor;

a first cache coupled between a memory and the processor; and

a second cache coupled between the memory and the processor;

wherein the computing device is configured to:

allocate a respective cache from the first cache and the second cache, in response a decision to execute one or more instructions;

access the memory via the respective cache during execution of the one or more instructions, to contain effects of the execution within the respective cache.

2. The computing device of claim 1 , wherein the respective cache is the second cache; and the processor is configured to assert, during the execution of the one or more instructions, a signal to block the first cache from changes.

3. The computing device of claim 2 , wherein the processor is configured to block, when the signal is asserted, the second cache from updating the memory.

4. The computing device of claim 3 , wherein the processor is configured to update the first cache according to the second cache, after the execution of the one or more instructions, in response to a determination that execution of the one or more instructions is to be performed.

5. The computing device of claim 3 , wherein the processor is configured to receive a signal that indicates completion of updating the first cache according to the second cache before executing instructions programmed for execution following the execution of the one or more instructions.

6. The computing device of claim 3 , wherein the processor is configured to update the second cache according to the first cache in response to a determination that execution of the one or more instructions is not to be performed.

7. The computing device of claim 3 , wherein the processor is configured to invalidate changes in the second cache in response to a determination that execution of the one or more instructions is not required.

8. The computing device of claim 1 , wherein the processor is configured to:

access the memory via the second cache, during the execution of one or more instructions; and

limit access to content in the second cache to the execution of the one or more instructions by the processor, during the execution of the one or more instructions.

9. The computing device of claim 8 , wherein the processor is configured to prohibit changing the first cache, during the execution of the one or more instructions.

10. The computing device of claim 1 , wherein the processor is configured to access content of the first cache via a cache coherency protocol.

11. A method comprising:

executing, by a processor, a set of instructions containing first instructions and second instructions, including:

executing, using a first cache coupled between a memory and the processor, the first instructions to evaluate a condition that determines whether to execute the second instructions; and

executing, by the processor prior to the condition being evaluated from execution of the first instructions, the second instructions using a second cache coupled between the memory and the processor, with effects of execution of the second instructions being limited within the second cache.

12. The method of claim 11 , further comprising:

determining whether the execution of the second instructions is required, after the execution of the second instructions.

13. The method of claim 12 , further comprising:

applying changes made by the second instructions in the second cache to the first cache, in response to determining the execution of the second instructions is required.

14. The method of claim 12 , further comprising:

invalidating content of the second cache, in response to determining the execution of the second instructions is not required.

15. The method of claim 12 , wherein limiting the effects of executing the second instructions includes:

prohibiting execution of the second instructions from changing the memory while allowing the speculative execution of the second instructions to change the second cache; and

prohibiting the execution of the second instructions from changing the first cache.

16. The method of claim 15 , further comprising:

prohibiting access to the second cache other than by the processor executing the second instructions.

17. A computing device, comprising:

memory;

a plurality of processors, including a first processor and a second processor; and

a plurality of sets of caches configured for the plurality of processors respectively to access the memory;

wherein the first processor in the plurality of processors is configured with access to a first cache configured for the second processor to access the memory; and

wherein the second processor is configured to be limited, during speculative execution of one or more instructions by the second processor, to access the memory via a second cache configured for the second processor and is prohibited from changing the memory via the second cache.

18. The computing device of claim 17 , wherein the first processor is prohibited from accessing the second cache configured for the second processor, during the speculative execution of the one or more instructions by the second processor.

19. The computing device of claim 18 , wherein after the speculative execution of the one or more instructions, changes in the second cache configured for the second processor are incorporated into the first cache configured for the second processor, in response to a determination to execute the one or more instructions.

20. The computing device of claim 19 , wherein before the speculative execution of the one or more instructions, the second cache configured for the second processor is synchronized with the first cache configured for the second processor.