Replay protected memory block data frame

1. A system comprising:

a memory device comprising a memory array and control circuitry, wherein the control circuitry is configured to:

receive a reduced Replay Protected Memory Block (RPMB) data frame defining an RPMB command from a host device, the RPMB command comprising an RPMB read or write command to be performed on non-volatile memory of the memory device;

maintain an RPMB command queue using the received RPMB command; and

perform the received RPMB command in order according to the RPMB command queue, wherein the RPMB command queue comprises multiple entries, including a queued RPMB read command and one or more RPMB write commands, and the memory device is configured to pre-fetch read data from a read address associated with the queued RPMB read command out of order with respect to one or more RPMB write commands while executing a current entry in the RPMB command queue; and

a host device configured to provide the reduced RPMB data frame to the memory device, the reduced RPMB data frame comprising:

header bytes;

data bytes following the header bytes; and

message authentication code (MAC) bytes following the data bytes,

wherein the memory device comprises an RPMB area and an RPMB circuit, wherein the RPMB circuit is configured to control access to the RPMB area and to maintain the RPMB command queue for the RPMB area using information from the reduced RPMB data frame including to implement a counter and to verify the order of an RPMB write command with the received write counter bytes and the counter.

2. The system of claim 1 , wherein the header bytes comprise, in order:

2 req/resp message type bytes;

2 result bytes;

2 block count bytes;

2 address bytes;

8 write counter bytes; and

16 nonce bytes.

3. The system of claim 1 , wherein the data bytes comprise a number (n) chunks of data, the n chunks of data consisting of all of the data bytes for a single read or write transfer, and the header bytes and the MAC bytes consisting all of the header bytes and MAC bytes for the single read or write transfer.

4. The system of claim 1 , wherein the memory device is configured to store the pre-fetched read data associated with the queued RPMB read command in volatile memory of the memory device while the control circuitry is performing the multiple entries in order according to the RPMB command queue.

5. The system of claim 4 , wherein the memory device is configured to provide the stored pre-fetched read data associated with the queued RPMB read command to the host device in order according to the RPMB command queue.

6. The system of claim 1 , wherein the memory device is configured to perform RPMB write commands from the multiple entries in the RPMB command queue in order according to the RPMB command queue and the counter, and to perform the RPMB read commands from the multiple entries in order according to the RPMB command queue using the pre-fetched read data.

7. The system of claim 1 , wherein the memory device comprises multiple memory die, each comprising respective RPMB areas, and

wherein the memory device is configured to maintain separate RPMB command queues for the respective RPMB areas.

8. The system of claim 1 , wherein the memory device comprises multiple memory die, each comprising respective RPMB areas, and

wherein each of the multiple memory die comprises control logic, wherein the control logic is configured to maintain RPMB command queues for each respective RPMB area.

9. The system of claim 1 , wherein the memory device comprises multiple RPMB areas and is configured to maintain separate RPMB command queues for each of the multiple RPMB areas, each of the multiple RPMB areas having a unique key, counter, and data area.

10. A method comprising:

receiving, at a memory device, a reduced Replay Protected Memory Block (RPMB) data frame from a host device, the reduced RPMB data frame defining an RPMB command comprising an RPMB read or write command to be performed on non-volatile memory of the memory device, the reduced RPMB data frame comprising:

header bytes;

data bytes following the header bytes; and

message authentication code (MAC) bytes following the data bytes,

controlling access to an RPMB area of the memory device and maintaining, using an RPMB circuit, an RPMB command queue for the RPMB area using information from the reduced RPMB data frame, including implementing a counter and verifying the order of an RPMB write command with the received write counter bytes and the counter, wherein the RPMB command queue comprises multiple entries, including a queued RPMB read command and one or more RPMB write commands, and

performing, using the memory device, RPMB commands in order according to the RPMB command queue comprising pre-fetching read data from a read address associated with the queued RPMB read command out of order with respect to one or more RPMB write commands, while executing a current entry in the RPMB command queue.

11. The method of claim 10 , wherein the header bytes comprise, in order:

2 req/resp message type bytes;

2 result bytes;

2 block count bytes;

2 address bytes;

8 write counter bytes; and

16 nonce bytes.

12. The method of claim 10 , wherein the data bytes comprise a number (n) chunks of data, the n chunks of data consisting of all of the data bytes for a single read or write transfer, and the header bytes and the MAC bytes consisting all of the header bytes and MAC bytes for the single read or write transfer.

13. The method of claim 10 , comprising:

storing the pre-fetched read data associated with the queued RPMB read command in volatile memory of the memory device while performing entries in the RPMB command queue in order according to the RPMB command queue.

14. The method of claim 13 , comprising:

providing the stored pre-fetched read data associated with the queued RPMB read command to the host device in order according to the RPMB command queue.

15. The method of claim 10 , comprising:

performing the one or more RPMB write commands from the multiple entries in the RPMB command queue in order according to the RPMB command queue and the counter; and

performing RPMB read commands from the multiple entries in order according to the RPMB command queue using the pre-fetched read data.

16. The method of claim 10 , wherein the memory device comprises multiple memory die, each comprising respective RPMB areas, and

wherein maintaining the RPMB command queue comprises maintaining separate RPMB command queues for the respective RPMB areas.

17. A system comprising:

a memory device comprising a memory array and control circuitry, wherein the control circuitry is configured to:

receive reduced Replay Protected Memory Block (RPMB) data frame from a host device, the reduced RPMB data frame defining an RPMB command comprising an RPMB read or write command to be performed on non-volatile memory of the memory device, the reduced RPMB data frame comprising:

header bytes;

data bytes following the header bytes; and

message authentication code (MAC) bytes following the data bytes,

wherein the memory device comprises an RPMB area and an RPMB circuit, wherein the RPMB circuit is configured to control access to the RPMB area and to maintain an RPMB command queue for the RPMB area using information from the reduced RPMB data frame, including to implement a counter and to verify the order of an RPMB write command with the received write counter bytes and the counter, wherein the RPMB command queue comprises multiple entries, including a queued RPMB read command and one or more RPMB write commands,

wherein the memory device is configured to and

wherein the memory device is configured to perform RPMB commands in order according to the RPMB command queue by pre-fetching read data from a read address associated with the queued RPMB read command out of order with respect to one or more RPMB write commands, while executing a current entry in the RPMB command queue.

18. The system of claim 17 , wherein the header bytes comprise, in order:

2 req/resp message type bytes;

2 result bytes;

2 block count bytes;

2 address bytes;

8 write counter bytes; and

16 nonce bytes,

wherein the data bytes comprise a number (n) chunks of data, the n chunks of data consisting of all of the data bytes for a single read or write transfer, and the header bytes and the MAC bytes consisting all of the header bytes and MAC bytes for the single read or write transfer.