IP Library Granted Patent US 11,700,214
Granted Patent B1
US 11,700,214 · App. 17/896,204 · Granted Jul 11, 2023

Network interface and buffer control method thereof

Inventors: Nobuhiro Yokoi (Tokyo, JP); Hiroka Ihara (Tokyo, JP)
Assignee: HITACHI, LTD.
H04L49/9052H04L49/9084
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Quick Facts
Patent No.
US 11,700,214
App. No.
17/896,204
Granted
Jul 11, 2023
Kind
B1
Abstract

A network interface includes a processor, memory, and a cache between the processor and the memory. The processor secures a plurality of buffers for storing transfer data in the memory, and manages an allocation order of available buffers of the plurality of buffers. The processor returns a buffer released after data transfer to a position before a predetermined position of the allocation order.

Claims (38)

1. A network interface comprising:

a processor;

a memory; and

a cache between the processor and the memory,

wherein the processor is configured to:

secure a plurality of buffers for storing transfer data in the memory,

manage an allocation order of available buffers of the plurality of buffers,

return a buffer released after data transfer to a position before a predetermined position of the allocation order, and

allocate a plurality of buffer groups in the memory,

wherein each of the plurality of buffer groups is composed of a plurality of buffers of the same size,

wherein the plurality of buffer groups have different buffer sizes from each other, and

wherein, when a transfer data size is equal to or less than a maximum buffer size of the different buffer sizes, the processor is configured to select a buffer group having a minimum buffer size among buffer sizes equal to or greater than the transfer data size to store the transfer data.

2. The network interface according to claim 1 ,

wherein the processor is configured to return the released buffer to a head position of the allocation order.

3. The network interface according to claim 1 ,

wherein the processor is configured to determine whether or not a buffer is required to be allocated for new transfer data based on an amount of buffer in use.

4. The network interface according to claim 1 ,

wherein when the transfer data size is greater than the maximum buffer size, the processor is configured to secure a new buffer area equal to or greater than the transfer data size.

5. The network interface according to claim 1 ,

wherein when the transfer data size is greater than the maximum buffer size, the processor is configured to divide the transfer data and allocate a buffer selected from the plurality of buffer groups to the divided transfer data.

6. The network interface according to claim 1 ,

wherein a maximum value of the number of buffers capable of being used simultaneously in each of the plurality of buffer groups is set.

7. The network interface according to claim 1 ,

wherein the processor is configured to:

determine whether or not a buffer is required to be allocated for new transfer data based on an amount of buffer in use when the transfer data size is equal to or less than the maximum buffer size, and

skip the determination when the transfer data size is greater than the maximum buffer size.

8. The network interface according to claim 1 ,

wherein the processor is configured to determine whether or not a buffer is required to be allocated for new transfer data based on an amount of buffer in use, and

set a maximum value of the number of buffers capable of being used simultaneously in the plurality of buffers.

9. A buffer control method in a network interface including a processor, a memory, and a cache between the processor and the memory, the buffer control method comprising:

by the processor:

securing a plurality of buffers for storing transfer data in the memory;

managing an allocation order of available buffers of the plurality of buffers;

returning a buffer released after data transfer to a position before a predetermined position of the allocation order; and

allocating a plurality of buffer groups in the memory,

wherein each of the plurality of buffer groups is composed of a plurality of buffers of the same size,

wherein the plurality of buffer groups have different buffer sizes from each other, and

wherein, when a transfer data size is equal to or less than a maximum buffer size of the different buffer sizes, the processor is configured to select a buffer group having a minimum buffer size among buffer sizes equal to or greater than the transfer data size to store the transfer data.

Assignments (2)
COMPANY SPLIT Recorded Aug 20, 2024
From: HITACHI, LTD.
To: HITACHI VANTARA, LTD.
Reel/Frame 069518/0761 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 26, 2022
From: YOKOI, NOBUHIRO; IHARA, HIROKA
To: HITACHI, LTD.
Reel/Frame 060909/0215 →
Priority Claims (1)
JP 2022-048675 · Mar 24, 2022 · national
Cited By (4)
US 12,362,961 US 12,375,431 US 12,621,251 US 12,634,363