Data latch circuit and semiconductor storage device
A data latch circuit includes a first transistor of a first conductivity type and a second transistor of the first conductivity type, and a third transistor of a second conductivity type and a fourth transistor of the second conductivity type. The third and fourth transistors are controlled to perform a first control operation to store data in the data latch circuit and to perform a second control operation to read the stored data.
1 . A data latch circuit comprising:
a first transistor of a first conductivity type and a second transistor of the first conductivity type; and
a third transistor of a second conductivity type and a fourth transistor of the second conductivity type, wherein
a source of the first transistor and a source of the second transistor are connected to a predetermined first reference voltage node,
a source of the third transistor is connected to a drain of the first transistor and a gate of the second transistor,
a source of the fourth transistor is connected to a drain of the second transistor and a gate of the first transistor,
a data wiring layer is connected to a drain of the third transistor and a drain of the fourth transistor,
a first gate layer is connected to a gate of the third transistor and not connected to the gate of the first transistor,
a second gate layer is connected to a gate of the fourth transistor and not connected to the gate of the second transistor, and
the third and fourth transistors are controlled according to a first control signal supplied to the first gate layer and a second control signal supplied to the second gate layer, respectively, to perform a first control operation to store data corresponding to a voltage applied to the data wiring layer in the data latch circuit and to perform a second control operation to read the stored data.
2 . The data latch circuit according to claim 1 , wherein voltage levels of the first gate layer and the second gate layer in a period during which the data is retained are lowered by any percentage in a range of 5 to 30% of uppermost voltage levels of the first gate layer and the second gate layer when the data is written.
3 . The data latch circuit according to claim 2 , further comprising:
first and second diffusion regions that are located apart from each other in a first direction on a semiconductor substrate;
a third gate layer connected to the gate of the first transistor; and
a fourth gate layer connected to the gate of the second transistor, wherein:
source and drain of each of the first transistor and the second transistor are located on the first diffusion region,
source and drain of each of the third transistor and the fourth transistor are located on the second diffusion region,
the first gate layer and the second gate layer extend in a second direction intersecting the first direction so as to overlap the second diffusion region in a stacking direction,
the data wiring layer extends in the first direction so as to overlap the first diffusion region and the second diffusion region in the stacking direction, and
the third gate layer and the fourth gate layer extend in the second direction, respectively, so as to overlap the first diffusion region in the stacking direction, and are located apart from each other in the first direction.
4 . The data latch circuit according to claim 2 , further comprising:
first, second, third, and fourth diffusion regions, that are located apart from each other in a second direction intersecting a first direction on a semiconductor substrate;
a third gate layer connected to the gate of the first transistor; and
a fourth gate layer connected to the gate of the second transistor, wherein:
the first, second, third, and fourth gate layers extend in the first direction, respectively, and are located apart from each other in the second direction, and
the data wiring layer is located between the second diffusion region and the third diffusion region and extends in the first direction.
5 . A data latch circuit comprising:
a first transistor of a first conductivity type and a second transistor of the first conductivity type;
a third transistor of a second conductivity type and a fourth transistor of the second conductivity type;
a first gate layer connected to a gate of the third transistor and a gate of the fourth transistor;
a first data wiring layer connected to a drain of the third transistor; and
a second data wiring layer connected to a drain of the fourth transistor, wherein
a source of the first transistor and a source of the second transistor are connected to a predetermined first reference voltage node,
a source of the third transistor is connected to a drain of the first transistor and a gate of the second transistor,
a source of the fourth transistor is connected to a drain of the second transistor and a gate of the first transistor,
the third and fourth transistors are controlled according to a control signal through the first gate layer to perform a first control operation to store data corresponding to voltages applied to the first and second data wiring layers in the data latch circuit and to perform a second control operation to read the stored data.
6 . The data latch circuit according to claim 5 , wherein a voltage level of the first gate layer in a period during which the data is retained in the data latch circuit is lowered by any percentage in a range of 5 to 30% of a power supply voltage level.
7 . The data latch circuit according to claim 6 , further comprising:
first and second diffusion regions that are located apart from each other in a second direction intersecting a first direction on a semiconductor substrate;
a third diffusion region located apart from the first diffusion region and the second diffusion region in the first direction;
a second gate layer connected to the gate of the first transistor; and
a third gate layer connected to the gate of the second transistor, wherein
source and drain of the first transistor are located on the first diffusion region,
source and drain of the second transistor are located on the second diffusion region,
source and drain of each of the third transistor and the fourth transistor are located on the third diffusion region,
the first gate layer extends in the second direction so as to overlap the first diffusion region and the second diffusion region in the stacking direction,
the second gate layer and the third gate layer extend in the second direction, respectively, so as to overlap the third diffusion region in the stacking direction, and are located apart from each other in the first direction,
the first data wiring layer extends in the first direction so as to overlap the first diffusion region and the third diffusion region in the stacking direction, and
the second data wiring layer extends in the first direction so as to overlap the second diffusion region and the third diffusion region in the stacking direction.
8 . The data latch circuit according to claim 6 , further comprising:
first, second, third, and fourth diffusion regions, that are located apart from each other in a second direction intersecting a first direction on a semiconductor substrate;
a first gate layer connected to the gate of the third transistor;
a second gate layer connected to the gate of the fourth transistor;
a third gate layer connected to the gate of the first transistor; and
a fourth gate layer connected to the gate of the second transistor, wherein:
source and drain of the first transistor are located on the first diffusion region,
source and drain of the second transistor are located on the fourth diffusion region,
source and drain of the third transistor are located on the second diffusion region,
source and drain of the fourth transistor are located on the third diffusion region,
the first data wiring layer extends in the first direction so as to overlap the second diffusion region in the stacking direction, and
the second data wiring layer extends in the first direction so as to overlap the third diffusion region in the stacking direction.
9 . A semiconductor storage device comprising:
a memory cell array having a bit line and first and second word lines; and
a data latch circuit configured to temporarily store data to be written to the memory cell array and the data read from the memory cell array, wherein the data latch circuit comprises:
a data storage circuit including at least two, but no more than four transistors of a first conductivity type, the at least two transistors of the first conductivity type including first and second transistors, and third and fourth transistors of a second conductivity type, and further wherein
a source of the first transistor and a source of the second transistor are connected to a predetermined first reference voltage node,
a source of the third transistor is connected to a drain of the first transistor and a gate of the second transistor,
a source of the fourth transistor is connected to a drain of the second transistor and a gate of the first transistor,
a data wiring layer is connected to the bit line, a drain of the third transistor, and a drain of the fourth transistor,
a first gate layer is connected to the first word line and a gate of the third transistor,
a second gate layer is connected to the second word line and a gate of the fourth transistor, and
the third and fourth transistors are controlled according to a first control signal supplied to the first gate layer and a second control signal supplied to the second gate layer, respectively, to perform a first control operation to store data corresponding to a voltage applied to the data wiring layer in the data latch circuit and to perform a second control operation to read the stored data.
10 . The semiconductor storage device according to claim 9 , wherein the data storage circuit includes four transistors of the first conductivity type.