IP Library Granted Patent US 11,960,403
Granted Patent B2
US 11,960,403 · App. 17/899,184 · Granted Apr 16, 2024

Variable execution time atomic operations

Inventors: Dean E. Walker (Allen, TX); Tony M. Brewer (Plano, TX)
Assignee: Micron Technology, Inc.
G06F12/084
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Quick Facts
Patent No.
US 11,960,403
App. No.
17/899,184
Granted
Apr 16, 2024
Kind
B2
Abstract

System and techniques for variable execution time atomic operations are described herein. When an atomic operation for a memory device is received, the run length of the operation is measured. If the run length is beyond a threshold, a cache line for the operation is locked while the operation runs. A result of the operation is queued until it can be written to the cache line. At that point, the cache line is unlocked.

Claims (62)

1. An apparatus for variable execution time atomic operations, the apparatus comprising:

a cache including a cache line; and

processing circuitry configured to:

receive an atomic operation that corresponds to an operation to be performed on memory in the apparatus;

detect that a run length of the atomic operation beyond a threshold;

lock the cache line for the memory in response to detecting that the run length is beyond the threshold;

enqueue a result of the atomic operation in a results queue;

write the cache line with the result in response to dequeuing the result from the results queue; and

unlock the cache line in response to writing the cache line with the result.

2. The apparatus of claim 1 , wherein, to lock the cache line, the processing circuitry is configured to set a tag for the cache line.

3. The apparatus of claim 2 , wherein the tag indicates that an atomic operation is pending.

4. The apparatus of claim 3 , wherein the tag is a bit at an index that corresponds to a pending atomic operation.

5. The apparatus of claim 1 , wherein the processing circuitry is configured to:

obtain a credit from an arbiter of the results queue; and

execute, in response to receiving the credit, the atomic operation to produce the result.

6. The apparatus of claim 5 , wherein the processing circuitry is configured to:

receive a second atomic operation at the apparatus;

detect that a second run length of the second atomic operation is beyond the threshold;

attempt to receive a second credit from the arbiter for the second atomic operation; and

refrain from starting execution of the second atomic operation upon failing to obtain the second credit from the arbiter.

7. The apparatus of claim 5 , wherein total credits available from the arbiter are equal to a number of entries available in the results queue.

8. The apparatus of claim 5 , wherein the processing circuitry is configured to return the credit to the arbiter upon receipt of the results after dequeuing from the results queue.

9. A method for variable execution time atomic operations, the method comprising:

receiving an atomic operation at a memory device, the atomic operation corresponding to an operation to be performed on memory in the memory device;

detecting that a run length of the atomic operation beyond a threshold;

locking a cache line for the memory in response to detecting that the run length is beyond the threshold;

enqueueing a result of the atomic operation in a results queue;

writing the cache line with the result in response to dequeuing the result from the results queue; and

unlocking the cache line in response to writing the cache line with the result.

10. The method of claim 9 , wherein locking the cache line includes setting a tag for the cache line.

11. The method of claim 10 , wherein the tag indicates that an atomic operation is pending.

12. The method of claim 11 , wherein the tag is a bit at an index that corresponds to a pending atomic operation.

13. The method of claim 9 , comprising:

obtaining a credit from an arbiter of the results queue; and

executing, in response to receiving the credit, the atomic operation to produce the result.

14. The method of claim 13 , comprising:

receiving a second atomic operation at the memory device;

detecting that a second run length of the second atomic operation is beyond the threshold;

attempting to receive a second credit from the arbiter for the second atomic operation; and

refraining from starting execution of the second atomic operation upon failing to obtain the second credit from the arbiter.

15. The method of claim 13 , wherein total credits available from the arbiter are equal to a number of entries available in the results queue.

16. The method of claim 13 , comprising returning the credit to the arbiter upon receipt of the results after dequeuing from the results queue.

17. A non-transitory machine readable medium including instructions for variable execution time atomic operations, the instructions, when executed by processing circuitry cause the processing circuitry to perform operations comprising:

receiving an atomic operation at a memory device, the atomic operation corresponding to an operation to be performed on memory in the memory device;

detecting that a run length of the atomic operation beyond a threshold;

locking a cache line for the memory in response to detecting that the run length is beyond the threshold;

enqueueing a result of the atomic operation in a results queue;

writing the cache line with the result in response to dequeuing the result from the results queue; and

unlocking the cache line in response to writing the cache line with the result.

18. The non-transitory machine readable medium of claim 17 , wherein locking the cache line includes setting a tag for the cache line.

19. The non-transitory machine readable medium of claim 18 , wherein the tag indicates that an atomic operation is pending.

20. The non-transitory machine readable medium of claim 19 , wherein the tag is a bit at an index that corresponds to a pending atomic operation.

21. The non-transitory machine readable medium of claim 17 , wherein the operations comprise:

obtaining a credit from an arbiter of the results queue; and

executing, in response to receiving the credit, the atomic operation to produce the result.

22. The non-transitory machine readable medium of claim 21 , wherein the operations comprise:

receiving a second atomic operation at the memory device;

detecting that a second run length of the second atomic operation is beyond the threshold;

attempting to receive a second credit from the arbiter for the second atomic operation; and

refraining from starting execution of the second atomic operation upon failing to obtain the second credit from the arbiter.

23. The non-transitory machine readable medium of claim 21 , wherein total credits available from the arbiter are equal to a number of entries available in the results queue.

24. The non-transitory machine readable medium of claim 21 , wherein the operations comprise returning the credit to the arbiter upon receipt of the results after dequeuing from the results queue.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 15, 2023
From: WALKER, DEAN E; BREWER, TONY M
To: MICRON TECHNOLOGY, INC.
Reel/Frame 062988/0824 →
Continuity (1)
Related Publication 20240070074A1 · Feb 29, 2024