Thermal extraction of single layer transfer integrated circuits
A FET IC structure made using a back-side access process that mitigates or eliminates thermal conductivity problems. In some embodiments, electrically-isolated thermal paths are formed adjacent the FET and configured to conduct heat laterally away from the FET to generally orthogonal thermal pathways, and thence to thermal pads externally accessible at the “top” of the completed IC. In some embodiments having a thermally-conductive handle wafer, electrically-isolated thermal paths are formed adjacent a FET and configured to conduct heat laterally away from the FET. Thermal vias are formed sufficiently so as to be in thermal contact with the handle wafer and with the conventional metallization layers of the device superstructure, at least one of which is in thermal contact with the lateral thermal paths. In some embodiments, the lateral thermal paths may use dummy gates configured to conduct heat laterally away from a FET to generally orthogonal thermal pathways.
1. A method of making a thermal conduction structure for an integrated circuit transistor device, including:
(a) fabricating at least one dummy gate electrically isolated from the transistor device by a gate oxide and in thermal contact with the transistor device;
(b) fabricating at least one thermal path electrically isolated from the transistor device and in thermal contact with at least one dummy gate, the at least one thermal path configured to convey heat from the transistor device to a heat sink.
2. The method of claim 1 , wherein the dummy gate comprises polysilicon.
3. The method of claim 1 , further including fabricating at least one thermal path at least in part by fabricating at least one metallization layer overlaying at least a portion of at least one dummy gate and extending laterally from the transistor device.
4. The method of claim 1 , wherein the integrated circuit transistor device is made using a silicon-on-insulator (SOI) process.