Time-synchronized input and/or output of signals with a selectable sampling rate

1. A method for synchronizing channels of a group of input and/or output channels of a plurality of modular input-output (I/O) circuits connected to a field-programmable gate array (FPGA) device, comprising:

synchronously initiating all the channels of the group of input and/or output channels of the plurality of modular I/O circuits at a standard sampling period;

configuring at least one channel of the group of input and/or output channels of the plurality of modular I/O circuits to have a different sampling period than at least one other channel of the group of input and/or output channels of the plurality of modular I/O circuits;

detecting an entry for a modified sampling period T Period for a first channel of the group of input and/or output channels of the plurality of modular I/O circuits;

detecting a current counter value T Counter ;

configuring the first channel for sampling using the modified sampling period;

establishing a waiting time of T Waiting clock cycles in accordance with T Waiting =T Period −mod(T Counter , T Period ), where mod(T Counter , T Period ) denotes the division remainder from the current counter value T Counter and the modified sampling period T Period , wherein the established waiting time synchronizes the first channel with a second channel of the group of input and/or output channels of the plurality of modular I/O circuits having a sampling period that is the same as the modified sampling period for the first channel of the group of input and/or output channels of the plurality of modular I/O circuits; and

initiating a first measurement on the first channel after the waiting time T Waiting , wherein the first measurement on the first channel is synchronized with a second measurement on the second channel;

wherein any two channels of the group of input and/or output channels of the plurality of modular I/O circuits which have a same sampling period are synchronized with one another.

2. The method according to claim 1 , wherein the processing of signals by one channel is delayed by an offset corresponding to a number of clock cycles of a clock generator;

wherein the method further comprises detecting an entry for a modified offset T Offset ; and

wherein determining the waiting time takes into account the modified offset in accordance with T Waiting =T Period −mod(T Counter , T Period )+T Offset .

3. The method according to claim 1 , wherein, to process a signal, channels of the group of input and/or output channels of the plurality of modular I/O circuits require a conversion duration T Min of more than one clock cycle; and

wherein the method further comprises extending the waiting time based on a time difference between a starting time T Counter +T Waiting for sampling at the modified sampling period and a starting time t Sample for a previous sampling period prior to the modification to the modified sampling period dropping below the conversion duration T Min in accordance with T Counter +T Waiting −t Sample <T Min .

4. The method according to claim 3 , wherein the required conversion duration T Min of a channel is stored in a storage device and is read out in the event of a modification to the sampling period for the channel; and

wherein the waiting time is extended by a multiple of n modified sampling period(s) in accordance with T Waiting =T Waiting +n·T Period , where n≥1.

5. The method according to claim 1 , wherein at least two input channels of the group of input and/or output channels of the plurality of modular I/O circuits receive the same signal, wherein the at least two input channels operate at the same sampling period and at a first constant offset between adjacent channels, and new constant offset is set based on a trigger condition being met.

6. The method according to claim 1 , wherein an input channel is operated at a first sampling period and is configured over to a second sampling period shorter than the first sampling period based on a trigger condition being met.

7. The method according to claim 1 , wherein the plurality of modular I/O circuits comprises at least two sub-circuits;

wherein each sub-circuit of the at least two sub-circuits has:

at least one input channel and/or at least one output channel,

a clock line to another sub-circuit, or

a distinct clock generator and a counter;

wherein synchronously initiating all the channels of the group of input and/or output channels of the plurality of modular I/O circuits at the standard sampling period comprises synchronizing the distinct clock generators and counters of the sub-circuits.

8. The method according to claim 7 , wherein each sub-circuit of the at least two sub-circuits is arranged on a separate field programmable gate array (FPGA) device.

9. The method according to claim 1 , wherein the configuration of the FPGA device is rewritten based on a simulation being initialized.

10. The method according to claim 9 , wherein the plurality of modular I/O circuits is connected to an operator computer on which a graphical user interface having a graphical depiction of the model to be simulated is executed, and wherein a block is depicted in the graphical user interface for at least one channel.

11. The method according to claim 10 , wherein the block is configured to receive signals from the simulated model and/or to output signals to the simulated model via ports;

wherein the ports include:

a port that indicates when an associated channel was initiated at a new sample period;

a port that indicates in how many clock cycles a newly set sample rate will become active; and/or

a port via which an entry is received for an offset of a channel by a number of clock cycles.

12. A non-transitory computer-readable medium having processor-executable instructions stored thereon for synchronizing channels of a group of input and/or output channels of a plurality of modular input-output (I/O) circuits connected to a field-programmable gate array (FPGA) device, wherein the processor-executable instructions, when executed, facilitate performance of the following:

synchronously initiating all the channels of the group of input and/or output channels of the plurality of modular I/O circuits at a standard sampling period;

configuring at least one channel of the group of input and/or output channels of the plurality of modular I/O circuits to have a different sampling period than at least one other channel of the group of input and/or output channels of the plurality of modular I/O circuits;

detecting an entry for a modified sampling period T Period for a first channel of the group of input and/or output channels of the plurality of modular I/O circuits;

detecting a current counter value T Counter ;

configuring the first channel for sampling using the modified sampling period;

establishing a waiting time of T Waiting clock cycles in accordance with T Waiting =T Period −mod(T Counter , T Period ), where mod(T Counter , T Period ) denotes the division remainder from the current counter value T Counter and the modified sampling period T Period , wherein the established waiting time synchronizes the first channel with a second channel of the group of input and/or output channels of the plurality of modular I/O circuits having a sampling period that is the same as the modified sampling period for the first channel of the group of input and/or output channels of the plurality of modular I/O circuits; and

initiating a first measurement on the first channel after the waiting time T Waiting , wherein the first measurement on the first channel is synchronized with a second measurement on the second channel;

wherein any two channels of the group of input and/or output channels of the plurality of modular I/O circuits which have a same sampling period are synchronized with one another.

13. An system, comprising:

a plurality of modular I/O circuits having a group of input and/or output channels;

a counter;

a programmable logic device connected to the plurality of modular I/O circuits, wherein the programmable logic device is configured to:

synchronously initiate all the channels of the group of input and/or output channels of the plurality of modular I/O circuits at a standard sampling period;

configure at least one channel of the group of input and/or output channels of the plurality of modular I/O circuits to have a different sampling period than at least one other channel of the group of input and/or output channels of the plurality of modular I/O circuits;

detect an entry for a modified sampling period T Period for a first channel of the group of input and/or output channels of the plurality of modular I/O circuits;

detect a current counter value T Counter of the counter;

configure the first channel for sampling using the modified sampling period;

establish a waiting time of T Waiting clock cycles in accordance with T Waiting =T Period −mod(T Counter , T Period ), where mod(T Counter , T Period ) denotes the division remainder from the current counter value T Counter and the modified sampling period T Period , wherein the established waiting time synchronizes the first channel with a second channel of the group of input and/or output channels of the plurality of modular I/O circuits having a sampling period that is the same as the modified sampling period for the first channel of the group of input and/or output channels of the plurality of modular I/O circuits; and

initiate a first measurement on the first channel after the waiting time T Waiting , wherein the first measurement on the first channel is synchronized with a second measurement on the second channel;

wherein any two channels of the group of input and/or output channels of the plurality of modular I/O circuits which have a same sampling period are synchronized with one another.

14. The interface system according to claim 13 , wherein the programmable logic device configured to calculate a division remainder according to a sub-configuration; and

wherein at least two channels of the group of input and/or output channels are configured to use a joint sub-configuration to calculate the division remainder.

15. The interface system according to claim 13 , wherein the programmable logic device configured to calculate a division remainder according to a sub-configuration; and

wherein the counter has a width selected according to predefined possible sample periods.