IP Library Patent Application 17939695
Patent Application
App. No. 17/939,695

SYSTEMS AND METHODS FOR CONVERTING DATA FROM INT-64 TO BOOLEAN FOR COMPUTATIONS

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Patent No.
US None
App. No.
17/939,695
Abstract

A method is disclosed for simplifying multi-party computation processes. The method includes converting a first n-bit-value data at a first computing device into a Boolean space, generating a first respective binary share of each respective first respective Boolean portion of the first n Boolean portions and a second respective binary share of each respective first respective Boolean portion of the first n Boolean portions, transmitting the second respective binary share to a second computing device, receiving, at the first computing device, a first respective binary share of each respective Boolean portion of a second n Boolean portions generated on the second computing device and performing a computation in Boolean space using the first respective binary share of each respective first Boolean portion of the first n Boolean portions and the first respective binary share of each respective Boolean portion of the second n Boolean portions.

Claims (46)

1 . A method comprising:

converting, via a processor, a first n-bit-value data at a first computing device into a Boolean space on a bit-by-bit basis to yield first n Boolean portions of the first n-bit-value, wherein n is greater than 1;

generating a first respective binary share of each respective first Boolean portion of the first n Boolean portions and a second respective binary share of each respective first Boolean portion of the first n Boolean portions;

transmitting the second respective binary share of each respective first Boolean portion of the first n Boolean portions to a second computing device;

receiving, at the first computing device and from the second computing device, a first respective binary share of each respective Boolean portion of a second n Boolean portions generated on the second computing device; and

performing, at the first computing device, a computation in Boolean space using the first respective binary share of each respective first Boolean portion of the first n Boolean portions and the first respective binary share of each respective Boolean portion of the second n Boolean portions to yield a first binary space resulting share.

2 . The method of claim 1 , further comprising:

checking a last significant bit of the first binary share of each respective first Boolean portion of the first n Boolean portions and the first binary share of each respective second Boolean portion of the second n Boolean portions to determine a respective sign.

3 . The method of claim 1 , further comprising:

switching a processing mode of a multi-party computation protocol to perform the computation in a Boolean mode.

4 . The method of claim 1 , wherein the first computing device uses an additive circuit comprising one of a ripple carry circuit or a brent kung circuit.

5 . The method of claim 1 , wherein the first respective binary share of each respective first Boolean portion of the first n Boolean portions is generated in connection with applying multi-secure party private computation private compare operation.

6 . The method of claim 1 , wherein the first respective binary share of each respective first Boolean portion of the first n Boolean portions represent an additive share of either a model or data that is to be kept private.

7 . The method of claim 1 , further comprising:

converting the first binary space resulting share into a multi-bit format to yield a multi-bit first resulting share for the first computing device.

8 . The method of claim 7 , further comprising:

generating, from the multi-bit first resulting share for the first computing device, a first multi-bit format share for the first computing device and a second multi-bit format share for the first computing device;

transmitting the first multi-bit format share for the first computing device to the second computing device;

receiving a first multi-bit format share for the second computing device from the second computing device; and

computing, based on the first multi-bit format share for the first computing device and the first multi-bit format share for the second computing device, a result in the multi-bit format.

9 . The method of claim 8 , wherein the multi-bit format is a 64 bit format and wherein n=64.

10 . The method of claim 8 , wherein performing, at the first computing device, the computation in Boolean space comprises applying a secure multi-party computation protocol in a Boolean mode and computing, based on the first multi-bit format share for the first computing device and the first multi-bit format share for the second computing device, a result in the multi-bit format is performed by applying the secure multi-party computation protocol in a multi-bit mode.

11 . A system comprising:

a processor; and

a computer-readable storage device storing instructions which, when executed by the processor, cause the processor to perform operations comprising:

converting a first n-bit-value data at a first computing device into a Boolean space on a bit-by-bit basis to yield first n Boolean portions of the first n-bit-value, wherein n is greater than 1;

generating a first respective binary share of each respective first Boolean portion of the first n Boolean portions and a second respective binary share of each respective first Boolean portion of the first n Boolean portions;

transmitting the second respective binary share of each respective first Boolean portion of the first n Boolean portions to a second computing device;

receiving, at the first computing device and from the second computing device, a first respective binary share of each respective Boolean portion of a second n Boolean portions generated on the second computing device; and

performing, at the first computing device, a computation in Boolean space using the first respective binary share of each respective first Boolean portion of the first n Boolean portions and the first respective binary share of each respective Boolean portion of the second n Boolean portions to yield a first binary space resulting share.

12 . The system of claim 10 , wherein the computer-readable storage device stores additional instructions which, when executed by the processor, cause the processor to perform operations further comprising:

checking a last significant bit of the first binary share of each respective first Boolean portion of the first n Boolean portions and the first binary share of each respective second Boolean portion of the second n Boolean portions to determine a respective sign.

13 . The system of claim 10 , wherein the computer-readable storage device stores additional instructions which, when executed by the processor, cause the processor to perform operations further comprising:

switching a processing mode of a multi-party computation protocol to perform the computation in a Boolean mode.

14 . The system of claim 10 , wherein the first computing device uses an additive circuit comprising one of a ripple carry circuit or a brent kung circuit.

15 . The system of claim 10 , wherein the first respective binary share of each respective first Boolean portion of the first n Boolean portions is generated in connection with applying multi-secure party private computation private compare operation.

16 . The system of claim 10 , wherein the first respective binary share of each respective first Boolean portion of the first n Boolean portions represent an additive share of either a model or data that is to be kept private.

17 . The system of claim 10 , wherein the computer-readable storage device stores additional instructions which, when executed by the processor, cause the processor to perform operations further comprising:

converting the first binary space resulting share into a multi-bit format to yield a multi-bit first resulting share for the first computing device.

18 . The system of claim 17 , wherein the computer-readable storage device stores additional instructions which, when executed by the processor, cause the processor to perform operations further comprising:

generating, from the multi-bit first resulting share for the first computing device, a first multi-bit format share for the first computing device and a second multi-bit format share for the first computing device;

transmitting the first multi-bit format share for the first computing device to the second computing device;

receiving a first multi-bit format share for the second computing device from the second computing device; and

computing, based on the first multi-bit format share for the first computing device and the first multi-bit format share for the second computing device, a result in the multi-bit format.

19 . The system of claim 18 , wherein the multi-bit format is a 64 bit format and wherein n=64.

20 . The system of claim 18 , wherein performing, at the first computing device, the computation in Boolean space comprises applying a secure multi-party computation protocol in a Boolean mode and computing, based on the first multi-bit format share for the first computing device and the first multi-bit format share for the second computing device, a result in the multi-bit format is performed by applying the secure multi-party computation protocol in a multi-bit mode.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 10, 2024
From: TRIPLEBLIND HOLDINGS, INC.
To: SELFIIE CORPORATION
Reel/Frame 068907/0556 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE SHOULD BE CORRECTED FROM TRIPLEBLIND HOLDING COMPANY TO TRIPLEBLIND HOLDINGS, INC. PREVIOUSLY RECORDED AT REEL: 67568 FRAME: 689. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 24, 2024
From: TRIPLEBLIND, INC.
To: TRIPLEBLIND HOLDINGS, INC.
Reel/Frame 068722/0100 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 30, 2024
From: POOREBRAHIM GILKALAYE, BABAK; DAS, RIDDHIMAN; STORM, GREG
To: TRIPLEBLIND, INC.
Reel/Frame 067559/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 30, 2024
From: TRIPLEBLIND, INC.
To: TRIPLEBLIND HOLDING COMPANY
Reel/Frame 067568/0689 →