Granted Patent B2

US 12,568,728 · App. 17/947,322 · Granted Mar 3, 2026

Inventors: Toni Lopez (Vaals, NL); Florent Monestier (Aachen, DE)

Assignee: LUMILEDS SINGAPORE PTE. LTD.

H10H29/49G09G3/32H01L25/0753H10H20/8312H10H20/857H10H29/39G09G2300/0426

Abstract

Claims (18)

1 . A CMOS power plane comprising:

a cathode redistribution ring having an inner portion and an outer portion, a die pixel area having a perimeter surrounded by the inner portion of the cathode redistribution ring, the outer portion comprising a common supply voltage Vled and a cathode current distribution area, the common supply voltage Vled interleaved with the cathode current distribution area; and

a plurality of cathode μbumps contacting the inner portion of the cathode redistribution ring along the perimeter of the die pixel area.

2 . The CMOS power plane of claim 1 , wherein the common supply voltage Vled and the cathode current distribution area are interleaved on two sides of the die pixel area.

3 . The CMOS power plane of claim 1 , wherein the common supply voltage Vled and the cathode current distribution area are interleaved on four sides of the die pixel area.

4 . The CMOS power plane of claim 1 , wherein there are at least three common supply voltage Vled interleaved with at least three cathode current distribution areas.

5 . The CMOS power plane of claim 1 , further comprising a plurality of PMOS transistors connected to the die pixel area.

6 . The CMOS power plane of claim 1 , further comprising a common cathode grid, wherein the plurality of cathode μbumps are electrically connected to the common cathode grid.

7 . The CMOS power plane of claim 1 , wherein the die pixel area comprises a plurality of pixels.

8 . A CMOS layout comprising:

a power plane on a substrate, the power plane having a plurality of alternating Vled contact areas and cathode contact areas uniformly dispersed along at least two sides of the power plane;

a cathode current redistribution ring extending along four sides of the power plane;

a plurality of pixels, the plurality of pixels having a corresponding p contact;

a plurality of cathode μbumps connecting each of the plurality of alternating Vled contact areas and cathode contact areas to the corresponding p contact of the plurality of pixels; and

a common cathode grid electrically connecting the plurality of pixels and the plurality of cathode μbumps.

9 . The CMOS layout of claim 8 , wherein the Vled contact areas and the cathode contact areas are interleaved on two sides.

10 . The CMOS layout of claim 8 , wherein there are at least three Vled contact areas alternating with at least three cathode contact areas.

11 . The CMOS layout of claim 8 , further comprising a plurality of PMOS transistors connected in parallel to at least one of the plurality of pixels.

Assignments (5)

Continuity (2)

References Cited (158)