Memory barrier elision for multi-threaded workloads
A system includes a memory, at least one physical processor in communication with the memory, and a plurality of threads executing on the at least one physical processor. A first thread of the plurality of threads is configured to execute a plurality of instructions that includes a restartable sequence. Responsive to a different second thread in communication with the first thread being pre-empted while the first thread is executing the restartable sequence, the first thread is configured to restart the restartable sequence prior to reaching a memory barrier.
1. A system comprising:
a memory;
a plurality of physical processors in communication with the memory;
a restartable sequence of instructions;
a data structure;
an operating system scheduler;
a file directory; and
a plurality of threads executing on the plurality of physical processors, wherein a first thread of the plurality of threads is configured to:
execute the restartable sequence of instructions, wherein the execution updates the data structure, the operating system scheduler updates a file in the file directory based on a change associated with a second thread of the plurality of threads, and the file includes a status of the second thread and an identification of a physical processor of the plurality of physical processors that the second thread is executing on;
receive a signal incident to the update to the file; and
responsive to receiving the signal, execute a read instruction associated with the restartable sequence of instructions at a particular time, wherein the particular time is based on a status of the first thread, wherein the status of the first thread indicates that the first thread and the second thread are executing on a same physical processor of the plurality of physical processors, or indicates that the first thread and the second thread are executing on different physical processors of the plurality of physical processors.
2. The system of claim 1 , wherein when the status of the first thread indicates that the first thread and the second thread are executing on the same physical processor, the first thread is configured to execute the read instruction within the restartable sequence of instructions without restarting the restartable sequence of instructions.
3. The system of claim 2 , wherein a write memory barrier is omitted when the status of the first thread indicates that the first thread and the second thread are executing on the same physical processor.
4. The system of claim 1 , wherein when the status of the first thread indicates that the first thread and the second thread are executing on the different physical processors, the first thread is configured to execute the read instruction after a write memory barrier by restarting the restartable sequence of instructions.
5. The system of claim 1 , wherein the status of the second thread is one of executing, sleeping, suspended, and in process of being killed.
6. The system of claim 1 , wherein executing a memory barrier takes a predetermined amount of time.
7. The system of claim 1 , wherein the file is a Linux/proc filesystem file that supports a poll system call and the directory has a file for each thread.
8. The system of claim 1 , wherein the first and second threads are both software threads.
9. The system of claim 8 , wherein the first and second threads are executing on different physical processors.
10. The system of claim 8 , wherein the first and second threads are executing on the same physical processor.
11. The system of claim 1 , wherein the second thread is executing on a physical CPU.
12. The system of claim 1 , wherein the second thread is executing on a logical CPU or a virtual CPU.
13. The system of claim 1 , wherein each thread of the plurality of threads registers to receive signals based on file updates from the operating system scheduler.
14. A method executed by a first thread of a plurality of threads executing on a plurality of physical processors comprising:
executing a restartable sequence of instructions, wherein the executing updates a data structure, an operating system scheduler updates a file in a file directory based on a change associated with a second thread of the plurality of threads, the data structure is distinct from the file directory, and the file includes a status of the second thread and an identification of a physical processor of the plurality of physical processors that the second thread is executing on;
receiving a signal incident to the update to the file; and
responsive to receiving the signal, executing a read instruction associated with the restartable sequence of instructions at a particular time, wherein the particular time is based on a status of the first thread, wherein the status of the first thread indicates that the first thread and the second thread are executing on a same physical processor of the plurality of physical processors, or indicates that the first thread and the second thread are executing on different physical processors of the plurality of physical processors.
15. The method of claim 14 , wherein when the status of the first thread indicates that the first thread and the second thread are executing on the different physical processors, the first thread is configured to execute the read instruction after a write memory barrier by restarting the restartable sequence of instructions.
16. The method of claim 14 , wherein the first and second threads are both software threads.
17. The method of claim 14 , wherein the file includes identification of at least two of a physical CPU, a logical CPU, or a virtual CPU.
18. The method of claim 14 , wherein when the status of the first thread indicates that the first thread and the second thread are executing on the same physical processor, the first thread is configured to execute the read instruction within the restartable sequence of instructions without restarting the restartable sequence of instructions.
19. The method of claim 18 , wherein a write memory barrier is omitted when the status of the first thread indicates that the first thread and the second thread are executing on the same physical processor.
20. A non-transitory computer-readable storage medium storing instructions which, when executed by a first thread of a plurality of threads on a processor of a plurality of processors executing the plurality of threads, cause the processor to:
execute a restartable sequence of instructions, wherein the execution updates a data structure, an operating system scheduler updates a file in a file directory based on a change associated with a second thread of the plurality of threads, the data structure is distinct from the file directory, and the file includes a status of the second thread and an identification of a physical processor of the plurality of physical processors that the second thread is executing on;
receive a signal incident to the update to the file; and
responsive to receiving the signal, execute a read instruction associated with the restartable sequence of instructions at a particular time, wherein the particular time is based on a status of the first thread, wherein the status of the first thread indicates that the first thread and the second thread are executing on a same physical processor of the plurality of physical processors, or indicates that the first thread and the second thread are executing on different physical processors of the plurality of physical processors.