Application specific integrated circuit accelerators
A tile including circuitry for use with machine learning models, the tile including: a first computational array of cells, in which the computational array of cells is a sub-array of a larger second computational array of cells; local memory coupled to the first computational array of cells; and multiple controllable bus lines, in which a first subset of the multiple controllable bus lines include multiple general purpose controllable bus lines couplable to the local memory.
1. An application specific integrated circuit comprising:
a plurality of tiles, wherein each tile of the plurality of tiles comprises a respective array of computational cells and respective local memory positioned proximate to the respective array of computational cells;
a plurality of controllable bus lines, wherein the plurality of controllable bus lines comprises a first group of general purpose controllable bus lines configured to provide data in four different directions among the plurality of tiles; and
a vector processing unit arranged to receive data outputs from the plurality of tiles,
wherein the plurality of tiles comprises a plurality of control elements, wherein each control element of each tile is configured to control whether data is transferred to the tile from the plurality of controllable bus lines or from the tile to the plurality of controllable bus lines,
wherein the plurality of controllable bus lines comprises a second group of bus lines configured to receive, from each tile of the plurality of tiles, data from the array of computational cells of the tile, and
wherein the vector processing unit is arranged to receive the data outputs from the second group of bus lines of each tile.
2. The application specific integrated circuit of claim 1 , wherein the respective array of computational cells of each tile is configured to perform multiplication and addition operations.
3. The application specific integrated circuit of claim 1 , wherein the plurality of tiles are arranged in a two-dimensional grid.
4. The application specific integrated circuit of claim 1 , wherein each tile of the plurality of tiles comprises a corresponding sub-array of a systolic array of cells.
5. The application specific integrated circuit of claim 1 , wherein each general purpose controllable bus line of the first group of general purpose controllable bus lines comprises a plurality of conveyer elements.
6. The application specific integrated circuit of claim 5 , wherein the plurality of conveyer elements comprises a plurality of flip-flops.
7. The application specific integrated circuit of claim 5 , wherein each general purpose controllable bus line of the first group of general purpose controllable bus lines is configured to transfer data by shifting, at a clock cycle, data from a first conveyer element of the general purpose controllable bus line to a second adjacent conveyer element of the general purpose controllable bus line.
8. The application specific integrated circuit of claim 7 , wherein each general purpose controllable bus line of the first group of general purpose controllable bus lines is configured to transfer the data from the first conveyer element to the second adjacent conveyer element on an edge of the clock cycle.
9. The application specific integrated circuit of claim 5 , wherein the plurality of conveyer elements are spaced apart at a same distance from one another.
10. The application specific integrated circuit of claim 5 , wherein each control element comprises a multiplexer or a demultiplexer.
11. The application specific integrated circuit of claim 10 , wherein each multiplexer and demultiplexer is coupled to a corresponding register configured to store a control signal that determines a state of the multiplexer or the demultiplexer to which the register is coupled.
12. The application specific integrated circuit of claim 1 , comprising a first additional tile, wherein the first additional tile is configured to initiate reading and writing operations with respect to transferring data to and from at least some of the plurality of tiles.
13. The application specific integrated circuit of claim 12 , comprising a second additional tile, wherein the second additional tile is configured to initiate reading and writing operations with respect to transferring data to and from at least some of the plurality of tiles.
14. The application specific integrated circuit of claim 13 , wherein the first additional tile and the second additional tile are in a same row of tiles.
15. The application specific integrated circuit of claim 12 , wherein the first additional tile comprises a corresponding array of computational cells and a corresponding local memory positioned proximate to the corresponding array of computational cells.
16. An application specific integrated circuit comprising:
a plurality of tiles, wherein each tile of the plurality of tiles comprises a respective array of computational cells and respective local memory positioned proximate to the respective array of computational cells;
a plurality of controllable bus lines, wherein the plurality of controllable bus lines comprises a first group of general purpose controllable bus lines configured to provide data in four different directions among the plurality of tiles,
wherein the plurality of tiles comprises a plurality of control elements, wherein each control element of each tile is configured to control whether data is transferred to the tile from the plurality of controllable bus lines or from the tile to the plurality of controllable bus lines,
wherein the plurality of controllable bus lines comprises a second group of bus lines configured to receive, from each tile of the plurality of tiles, data from the array of computational cells of the tile,
wherein each general purpose controllable bus line of the first group of general purpose controllable bus lines comprises a plurality of conveyer elements,
wherein the plurality of conveyer elements comprises a plurality of flip-flops.
17. The application specific integrated circuit of claim 16 , wherein each general purpose controllable bus line of the first group of general purpose controllable bus lines is configured to transfer data by shifting, at a clock cycle, data from a first conveyer element of the general purpose controllable bus line to a second adjacent conveyer element of the general purpose controllable bus line.
18. An application specific integrated circuit comprising:
a plurality of tiles, wherein each tile of the plurality of tiles comprises a respective array of computational cells and respective local memory positioned proximate to the respective array of computational cells;
a plurality of controllable bus lines, wherein the plurality of controllable bus lines comprises a first group of general purpose controllable bus lines configured to provide data in four different directions among the plurality of tiles,
wherein the plurality of tiles comprises a plurality of control elements, wherein each control element of each tile is configured to control whether data is transferred to the tile from the plurality of controllable bus lines or from the tile to the plurality of controllable bus lines,
wherein the plurality of controllable bus lines comprises a second group of bus lines configured to receive, from each tile of the plurality of tiles, data from the array of computational cells of the tile;
a first additional tile, wherein the first additional tile is configured to initiate reading and writing operations with respect to transferring data to and from at least some of the plurality of tiles; and
a second additional tile, wherein the second additional tile is configured to initiate reading and writing operations with respect to transferring data to and from at least some of the plurality of tiles.
19. The application specific integrated circuit of claim 18 , wherein the first additional tile and the second additional tile are in a same row of tiles.
20. The application specific integrated circuit of claim 18 , wherein the first additional tile comprises a corresponding array of computational cells and a corresponding local memory positioned proximate to the corresponding array of computational cells.