Buffer circuitry for store to load forwarding

1. A method comprising:

receiving a first store instruction, the first store instruction comprising a first target address, a first mask, and a first data structure;

storing the first target address, the first mask, and the first data structure as a first entry within a first store buffer location of store buffer locations of a store buffer, each of the store buffer locations configured to store a respective entry;

storing a first entry identification associated with the first store buffer location within a first age buffer location of age buffer locations of an age buffer, each of the age buffer locations configured to store a respective entry identification, wherein an order of the entry identifications within the age buffer locations differs from an order of the entries within the store buffer locations;

receiving a load instruction comprising a second target address, a second mask, and a second data structure;

generating an address vector based on the second target address and the first target address and a mask vector based on the second mask and the first mask;

sorting the address vector and the mask vector based on the age buffer; and

outputting the first data structure based on the sorted address vector and the sorted mask vector.

2. The method of claim 1 , wherein each of the store buffer locations is associated with a respective one of the entry identifications.

3. The method of claim 2 , wherein the age buffer locations are configured to store the entry identifications of the store buffer locations.

4. The method of claim 3 , wherein the entry identifications stored within the age buffer locations are ordered based on an age of each of the entry identifications.

5. The method of claim 1 further comprising:

receiving a second store instruction, the second store instruction comprising a second target address, a second mask, and a second data structure;

storing the second target address, the second mask, and the second data structure within a second store buffer location of the store buffer; and

storing a second entry identification associated with the second store buffer location within the age buffer, wherein the first entry identification and the second entry identification are ordered within the age buffer based on relative age of the first store instruction and the second store instruction.

6. The method of claim 1 further comprising:

extracting the first data structure based on a comparison between the second target address and the first target address, a comparison between the second mask and the first mask, and based on the sorted address vector and the sorted mask vector.

7. The method of claim 6 , wherein

generating the address vector comprises comparing the second target address with a target address within each store buffer location of the store buffer, and

wherein the method further comprises generating mask vectors by comparing the second mask with a mask of each of the store buffer locations, and wherein the mask vectors comprise the mask vector.

8. The method of claim 7 , wherein sorting the address vector and the mask vector comprises

ordering the address vector and the mask vectors based on the order of the entry identifications within the age buffer locations of the age buffer.

9. A processing system comprising:

a memory;

a processor configured to access the memory via transactions; and

buffer circuitry comprising a store buffer and an age buffer, the buffer circuitry configured to:

receive a first store instruction, the first store instruction comprising a first target address, a first mask, and a first data structure;

store the first target address, the first mask, and the first data structure as a first entry within a first store buffer location of store buffer locations of the store buffer, each of the store buffer locations configured to store a respective entry; and

store a first entry identification associated with the first store buffer location within a first age buffer location of age buffer locations of the age buffer, each of the age buffer locations configured to store a respective entry identification, wherein an order of the entry identifications within the age buffer locations differs from an order of the entries within the store buffer locations;

receive a load instruction comprising a second target address, a second mask, and a second data structure;

generate an address vector based on the second target address and the first target address and a mask vector based on the second mask and the first mask;

sort the address vector and the mask vector based on the age buffer; and

output the first data structure based on the sorted address vector and the sorted mask vector.

10. The processing system of claim 9 , wherein each of the store buffer locations is associated with a respective one of the entry identifications.

11. The processing system of claim 10 , wherein the age buffer locations are configured to store the entry identifications of the store buffer locations.

12. The processing system of claim 11 , wherein the entry identifications stored within the age buffer locations are ordered based on an age of each of the entry identifications.

13. The processing system of claim 9 , wherein the buffer circuitry is further configured to:

receive a second store instruction, the second store instruction comprising a second target address, a second mask, and a second data structure;

store the second target address, the second mask, and the second data structure within a second store buffer location of the store buffer; and

store a second entry identification associated with the second store buffer location within the age buffer, wherein the first entry identification and the second entry identification are ordered within the age buffer based on relative age of the first store instruction and the second store instruction.

14. The processing system of claim 9 , wherein the buffer circuitry is further configured to:

extract the first data structure based on a comparison between the second target address and the first target address, and a comparison between the second mask and the first mask, and the sorted address vector and the sorted mask vector.

15. The processing system of claim 14 , wherein

generating the address vector comprises comparing the second target address with a target address within each store buffer locations of the store buffer, and

wherein the buffer circuitry is further configured to generate mask vectors by comparing the second mask with the first mask of each of the store buffer locations, and wherein the mask vectors comprise the mask vector.

16. The processing system of claim 15 , wherein the buffer circuitry is further configured to:

order the address vector and the mask vectors based on the order of the entry identifications within the age buffer locations of the age buffer.

17. A buffer circuitry configured to:

store first target addresses, first masks, and first data structures of store instructions as entries within buffer locations of a first buffer;

store entry identifications associated with the buffer locations of the first buffer within a second buffer, wherein the entry identifications are ordered based on an age of the store instructions, and an order of the entry identifications within the second buffer differs from an order of the entries within the first buffer;

receive a load instruction, the load instruction comprising a second target address, a second mask, and a second data structure;

generate an address vector based on the second target address with each of the first target addresses and mask vectors based on the second mask with each of the first masks;

order the address vector and the mask vectors based on the order of the entry identifications within buffer locations of the second buffer; and

output one of the first data structures based on the ordered address vector and the ordered mask vectors.

18. The buffer circuitry of claim 17 , wherein to:

generating the address vector comprises comparing the second target address with each of the first target addresses within the buffer locations of the first buffer; and

generating the mask vectors comprises comparing the second mask with the each of the first masks within the buffer locations of the first buffer.

19. The buffer circuitry of claim 17 , wherein outputting one of the first data structures is further based on the order of the entry identifications within the second buffer.

20. The method of claim 1 , wherein the first mask defines one or more bits to be maintained and one or more bits to be cleared.